Showing papers on "CMOS published in 2022"

Two-Dimensional Violet Phosphorus: A p-Type Semiconductor for (Opto)electronics.

Abstract: The synthesis of novel two-dimensional (2D) materials displaying an unprecedented composition and structure via the exfoliation of layered systems provides access to uncharted properties. For application in optoelectronics, a vast majority of exfoliated 2D semiconductors possess n-type or more seldom ambipolar characteristics. The shortage of p-type 2D semiconductors enormously hinders the extensive engineering of 2D devices for complementary metal oxide semiconductors (CMOSs) and beyond CMOS applications. However, despite the recent progress in the development of 2D materials endowed with p-type behaviors by direct synthesis or p-doping strategies, finding new structures is still of primary importance. Here, we report the sonication-assisted liquid-phase exfoliation of violet phosphorus (VP) crystals into few-layer-thick flakes and the first exploration of their electrical and optical properties. Field-effect transistors based on exfoliated VP thin films exhibit a p-type transport feature with an Ion/Ioff ratio of 104 and a hole mobility of 2.25 cm2 V-1 s-1 at room temperature. In addition, the VP film-based photodetectors display a photoresponsivity (R) of 10 mA W-1 and a response time down to 0.16 s. Finally, VP embedded into CMOS inverter arrays displays a voltage gain of ∼17. This scalable production method and high quality of the exfoliated material combined with the excellent optoelectronic performances make VP an enticing and versatile p-type candidate for next-generation more-than-Moore (opto)electronics.

Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments

Abstract: With the rapid advancement of CMOS technologies, nano-scale CMOS latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations. First, this paper proposes a novel latch design, namely QNUTL that can completely tolerate MNUs such as double-node upsets, triple-node upsets (TNUs), and even quadruple-node upsets (QNUs). The latch is mainly constructed from three dual-interlocked-storage-cells (DICEs) and a triple-level soft-error interceptive module (SIM) that consists of six 2-input C-elements. Due to the single-node-upset self-recoverability of DICEs and the soft-error interception of the SIM, the latch can completely tolerate any QNU. Next, by replacing the DICEs in the QNUTL latch by clock-gating (CG) based ones, a QNUTL-CG latch is proposed to significantly reduce power consumption. Simulation results demonstrate the MNU-tolerance of the proposed latches. Moreover, owing to the use of a high-speed transmission path, clock-gating, and a few transistors, the proposed QNUTL-CG latch has low overhead in terms of area, D-Q delay, CLK-Q delay, and setup time, compared with the state-of-the-art TNU-tolerant latch (TNUTL) which is not QNU-tolerant.

Integrated silicon carbide electro-optic modulator

Abstract: Owing to its attractive optical and electronic properties, silicon carbide is an emerging platform for integrated photonics. However an integral component of the platform is missing-an electro-optic modulator, a device which encodes electrical signals onto light. As a non-centrosymmetric crystal, silicon carbide exhibits the Pockels effect, yet a modulator has not been realized since the discovery of this effect more than three decades ago. Here we design, fabricate, and demonstrate a Pockels modulator in silicon carbide. Specifically, we realize a waveguide-integrated, small form-factor, gigahertz-bandwidth modulator that operates using complementary metal-oxide-semiconductor (CMOS)-level voltages on a thin film of silicon carbide on insulator. Our device is fabricated using a CMOS foundry compatible fabrication process and features no signal degradation, no presence of photorefractive effects, and stable operation at high optical intensities (913 kW/mm2), allowing for high optical signal-to-noise ratios for modern communications. Our work unites Pockels electro-optics with a CMOS foundry compatible platform in silicon carbide.

A 14-b 20-MS/s 78.8 dB-SNDR Energy-Efficient SAR ADC With Background Mismatch Calibration and Noise-Reduction Techniques for Portable Medical Ultrasound Systems

Abstract: This paper presents a 14-b 20-MS/s energy-efficient SAR ADC in 65-nm CMOS technology for portable medical ultrasound systems. To break the limitation of the ADC linearity on the DAC size in a SAR ADC, a background mismatch calibration technique is employed. As a result, the thermal noise will be the major constraint for the DAC size. In addition, a compact noise-reduction technique is proposed to alleviate the adverse impact of the input-referred comparator noise on the effective resolution. Moreover, a 2.5-V on-chip LDO, which serves as the reference generator for the ADC core, is also integrated to guarantee the reference accuracy and to suppress the supply noise. To reduce the capacitive load of the comparator and boost the comparison speed, a low fan-in SAR logic is also designed. With the proposed mismatch calibration technique and the noise-reduction technique activated, measured results indicate that the peak signal-to-noise-and-distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) achieve 78.8 dB and 95.4 dB, respectively. At 20 MS/s, the ADC consumes 6.8mW from its 1.2 V/3.3V supplies in total, leading to an SNDR-based Schreier FOM of 170.5 dB at Nyquist. The active area of the ADC is 450 × 540μm2.

Ferroelectric-based synapses and neurons for neuromorphic computing

Abstract: The shift towards a distributed computing paradigm, where multiple systems acquire and elaborate data in real-time, leads to challenges that must be met. In particular, it is becoming increasingly essential to compute on the edge of the network, close to the sensor collecting data. The requirements of a system operating on the edge are very tight: power efficiency, low area occupation, fast response times, and on-line learning. Brain-inspired architectures such as Spiking Neural Networks (SNNs) use artificial neurons and synapses that simultaneously perform low-latency computation and internal-state storage with very low power consumption. Still, they mainly rely on standard complementary metal-oxide-semiconductor (CMOS) technologies, making SNNs unfit to meet the aforementioned constraints. Recently, emerging technologies such as memristive devices have been investigated to flank CMOS technology and overcome edge computing systems' power and memory constraints. In this review, we will focus on ferroelectric technology. Thanks to its CMOS-compatible fabrication process and extreme energy efficiency, ferroelectric devices are rapidly affirming themselves as one of the most promising technology for neuromorphic computing. Therefore, we will discuss their role in emulating neural and synaptic behaviors in an area and power-efficient way.

A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR

Abstract: This article presents a 50-Gb/s optical transmitter (TX), consisting of a 40-nm distributed CMOS driver and a 180-nm silicon-photonic modulator. A lumped-segment Mach–Zehnder modulator (LS-MZM) is developed for high bandwidth (BW) four-level pulse amplitude (PAM-4) modulation. A multi-segment driver with limiting outputs is co-designed, which is distributed into each LS-MZM segment. By grouping these LS-MSM segments in a thermometer code, high-linearity modulation is realized without the need of power-hungry high-swing linear drivers. To improve the optical PAM-4 signal integrity, in-segment multiplexing along with clock phase interpolation is adopted to synchronize the electrical and optical signals across all segments. The hybrid coupling between the driver and modulator is devised to boost the BW of the high-speed data path, while a half-rate clock and data recovery (CDR) circuit is integrated to remove the accumulated jitter. Measurements show that the TX exhibits an extinction ratio (ER) of up to 9.8 dB and a 0.99 ratio of the level mismatch. A figure-of-merit (FoM) of 1.39 pJ/bit/dB corresponds to a 682-mW power, which can be further reduced by 40%, at the cost of a degraded ER of 4 dB. The PAM-4 CDR helps to achieve $< 10^{-12}$ BER and >0.1- $\text{U}I_{\mathrm {pp}}$ jitter tolerance (JTOL) from 10 to 100 MHz.

Scaling up silicon photonic-based accelerators: Challenges and opportunities

Abstract: Digital accelerators in the latest generation of CMOS processes support multiply and accumulate (MAC) operations at energy efficiencies spanning 10-to-100~fJ/Op. But the operating speed for such MAC operations are often limited to a few hundreds of MHz. Optical or optoelectronic MAC operations on today's SOI-based silicon photonic integrated circuit platforms can be realized at a speed of tens of GHz, leading to much lower latency and higher throughput. In this paper, we study the energy efficiency of integrated silicon photonic MAC circuits based on Mach-Zehnder modulators and microring resonators. We describe the bounds on energy efficiency and scaling limits for NxN optical networks with today's technology, based on the optical and electrical link budget. We also describe research directions that can overcome the current limitations.

Growth of high-quality semiconducting tellurium films for high-performance p-channel field-effect transistors with wafer-scale uniformity

Abstract: Abstract Achieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm 2 V −1 s −1 and an I ON/OFF ratio of 5.8 × 10 5 with 4-inch wafer-scale integrity on a SiO 2 /Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.

Perspective of 2D Integrated Electronic Circuits: Scientific Pipe Dream or Disruptive Technology?

Abstract: Within the last decade, considerable efforts have been devoted to fabricating transistors utilizing 2D semiconductors. Also, small circuits consisting of a few transistors have been demonstrated, including inverters, ring oscillators, and static random access memory cells. However, for industrial applications, both time‐zero and time‐dependent variability in the performance of the transistors appear critical. While time‐zero variability is primarily related to immature processing, time‐dependent drifts are dominated by charge trapping at defects located at the channel/insulator interface and in the insulator itself, which can substantially degrade the stability of circuits. At the current state of the art, 2D transistors typically exhibit a few orders of magnitude higher trap densities than silicon devices, which considerably increases their time‐dependent variability, resulting in stability and yield issues. Here, the stability of currently available 2D electronics is carefully evaluated using circuit simulations to determine the impact of transistor‐related issues on the overall circuit performance. The results suggest that while the performance parameters of transistors based on certain material combinations are already getting close to being competitive with Si technologies, a reduction in variability and defect densities is required. Overall, the criteria for parameter variability serve as guidance for evaluating the future development of 2D technologies.

CMOS-compatible compute-in-memory accelerators based on integrated ferroelectric synaptic arrays for convolution neural networks

Abstract: Convolutional neural networks (CNNs) have gained much attention because they can provide superior complex image recognition through convolution operations. Convolution processes require repeated multiplication and accumulation operations, which are difficult tasks for conventional computing systems. Compute-in-memory (CIM) that uses parallel data processing is an ideal device structure for convolution operations. CIM based on two-terminal synaptic devices with a crossbar structure has been developed, but unwanted leakage current paths and the high-power consumption remain as the challenges. Here, we demonstrate integrated ferroelectric thin-film transistor (FeTFT) synaptic arrays that can provide efficient parallel programming and data processing for CNNs by the selective and accurate control of polarization in the ferroelectric layer. In addition, three-terminal FeTFTs can act as both nonvolatile memory and access device, which tackle issues from two-terminal devices. An integrated FeTFT synaptic array with parallel programming capabilities can perform convolution operations to extract image features with a high-recognition accuracy.

Hybrid architecture based on two-dimensional memristor crossbar array and CMOS integrated circuit for edge computing

Abstract: Abstract The fabrication of integrated circuits (ICs) employing two-dimensional (2D) materials is a major goal of semiconductor industry for the next decade, as it may allow the extension of the Moore’s law, aids in in-memory computing and enables the fabrication of advanced devices beyond conventional complementary metal-oxide-semiconductor (CMOS) technology. However, most circuital demonstrations so far utilizing 2D materials employ methods such as mechanical exfoliation that are not up-scalable for wafer-level fabrication, and their application could achieve only simple functionalities such as logic gates. Here, we present the fabrication of a crossbar array of memristors using multilayer hexagonal boron nitride (h-BN) as dielectric, that exhibit analog bipolar resistive switching in >96% of devices, which is ideal for the implementation of multi-state memory element in most of the neural networks, edge computing and machine learning applications. Instead of only using this memristive crossbar array to solve a simple logical problem, here we go a step beyond and present the combination of this h-BN crossbar array with CMOS circuitry to implement extreme learning machine (ELM) algorithm. The CMOS circuit is used to design the encoder unit, and a h-BN crossbar array of 2D hexagonal boron nitride (h-BN) based memristors is used to implement the decoder functionality. The proposed hybrid architecture is demonstrated for complex audio, image, and other non-linear classification tasks on real-time datasets.

A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push–Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM

Abstract: This brief describes an integer-N-type-II sub-sampling phase-locked loop (SS-PLL) incorporating a push–pull sub-sampling phase detector to significantly suppress the spur-induced binary frequency shift keying modulation (BFSK) effect and a low-power fast-locking frequency-locked loop (FLL) to shorten the settling time. Prototyped in 65-nm CMOS, the SS-PLL at 3.3 GHz shows a reference spur of −82.2 dBc, an integrated jitter of 64.9 fs_rms (1 kHz to 40 MHz), and an in-band phase noise (PN) of −128.4 dBc/Hz at 1-MHz offset. The corresponding jitter power figure of merit (FOM) is −255 dB. The entire SS-PLL consumes 7.5 mW, with only $90~\mu \text{W}$ associated with the FLL.

Spin Orbit Torque-Assisted Magnetic Tunnel Junction-Based Hardware Trojan

Abstract: With the advancement of beyond-CMOS devices to keep Moore’s law alive, several emerging devices have found application in a wide range of applications. Spintronic devices offer low power, non-volatility, inherent spatial and temporal randomness, simplicity of integration with a silicon substrate, etc. This makes them a potential candidate for next-generation hardware options. This work explores the giant spin Hall effect (GSHE)-driven spin-orbit torque (SOT) magnetic tunnel junction (MTJ) as a potential candidate for creating an externally triggered hardware Trojan and insertion into logic-locked hardware security considering the effect of process and temperature variations.

A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

Abstract: In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tree-based structure improves the CMRR of the proposed amplifier with respect to the conventional OTA architectures and allows achievement of a reasonable CMRR even at supply voltages as low as 0.3 V and without tail current generators which cannot be used in ULV circuits. The bias currents and the static output voltages of all the stages implementing the architecture are accurately set through the gate terminals of biasing transistors in order to guarantee good robustness against PVT variations. The proposed architecture and the implementing stages are investigated from an analytical point of view and design equations for the main performance metrics are presented to provide insight into circuit behavior. A 0.3 V supply voltage, subthreshold, ultra-low-power (ULP) OTA, based on the proposed tree-based architecture, was designed in a commercial 130 nm CMOS process. Simulation results show a dc gain higher than 52 dB with a gain-bandwidth product of about 35 kHz and reasonable values of CMRR and PSRR, even at such low supply voltages and considering mismatches. The power consumption is as low as 21.89 nW and state-of-the-art small-signal and large-signal FoMs are achieved. Extensive parametric and Monte Carlo simulations show the robustness of the proposed circuit to PVT variations and mismatch. These results confirm that the proposed OTA is a good candidate to implement ULV, ULP, high performance analog building blocks for directly harvested IoT nodes.

Reconfigurable Field Effect Transistors: A Technology Enablers Perspective

Abstract: With classical scaling of CMOS transistors according to Dennard’s scaling rules running out of steam, new possibilities to increase the functionality of an integrated circuit at a given footprint are becoming more and more desirable. Among these approaches the possibility to reconfigure the functionality of a transistor on the single devices level stand out, as by such an approach the same physical circuitry is enabled to perform different tasks in different configurations of the circuit. Reconfigurable transistors that allow the reconfiguration from a p-channel to an n-channel transistor and vice versa have emerged as an important example of such devices. The basic concepts required to built such devices have been proposed more then 20 years ago and the field has continuously developed ever since. In this article first the basic classification of reconfigurable field effect transistors is reviewed an described form a new angle. In the second part the important technology enablers to construct reconfigure field effect transistors are examined. Further the historical development, starting at the proposal of the main concepts up to the current status of device and circuit development are described. The most important additional features that have been introduced in the last years in order to even further increase the flexibility of the devices are discussed. Finally the application potential of reconfigurable transistors is described placing the spotlight on hardware security and neuromorphic applications.

In-sensor optoelectronic computing using electrostatically doped silicon

Abstract: Complementary metal–oxide–semiconductor (CMOS) image sensors allow machines to interact with the visual world. In these sensors, image capture in front-end silicon photodiode arrays is separated from back-end image processing. To reduce the energy cost associated with transferring data between the sensing and computing units, in-sensor computing approaches are being developed where images are processed within the photodiode arrays. However, such methods require electrostatically doped photodiodes where photocurrents can be electrically modulated or programmed, and this is challenging in current CMOS image sensors that use chemically doped silicon photodiodes. Here we report in-sensor computing using electrostatically doped silicon photodiodes. We fabricate thousands of dual-gate silicon p–i–n photodiodes, which can be integrated into CMOS image sensors, at the wafer scale. With a 3 × 3 network of the electrostatically doped photodiodes, we demonstrate in-sensor image processing using seven different convolutional filters electrically programmed into the photodiode network. A network of dual-gate silicon p–i–n photodiodes, which are compatible with complementary metal–oxide–semiconductor fabrication processes, can perform in-sensor image processing by being electrically programmed into convolutional filters.

Selectivity mechanisms in resistive-type metal oxide heterostructural gas sensors

Abstract: Resistive-type semiconducting metal oxide (SMOX) sensors offer exciting possibilities for designing sensing systems that can detect extremely low concentrations of gasses relevant for industrial applications, environmental monitoring, and human health and safety. Research on this technology has produced sensors with high response, but the ability to predictively design sensing systems for specific applications requires improvements in selective detection. Gas selectivity is necessary to differentiate between multiple gas species that may be present in a given application. This has prevented wide-spread use of this technology in real-world settings. In this work, studies on gas selectivity in semiconducting metal oxide sensors are reviewed with specific emphasis on heterojunctions and fundamental sensing mechanisms. Concepts relating both to receptive and transduction sensor mechanisms are explained. The effects due to gas surface interactions and electronic equilibration are compared and discussed. Both modeling efforts and experimental literature are presented to explain fundamental mechanisms that control sensor behavior. Sensor selectivity is examined to further both fundamental understanding as well as increase real-world applications of semiconducting metal oxides.

Review of Quanta Image Sensors for Ultralow-Light Imaging

Abstract: The quanta image sensor (QIS) is a photon-counting image sensor that has been implemented using different electron devices, including impact ionization-gain devices, such as the single-photon avalanche detectors (SPADs), and low-capacitance, high conversion-gain devices, such as modified CMOS image sensors (CIS) with deep subelectron read noise and/or low noise readout signal chains. This article primarily focuses on CIS QIS, but recent progress of both types is addressed. Signal processing progress, such as denoising, critical to improving apparent signal-to-noise ratio, is also reviewed as an enabling coinnovation.

A Low-Noise CMOS SPAD Pixel With 12.1 Ps SPTR and 3 Ns Dead Time

Abstract: Single-photon avalanche diodes (SPADs) have become the sensor of choice in many applications whenever high sensitivity, low noise, and sharp timing performance are required, simultaneously. Recently, SPADs designed in CMOS technology, have yielded moderately good performance in these parameters, but never equaling their counterparts fabricated in highly customized, non-standard technologies. The arguments in favor of CMOS-compatible SPADs were miniaturization, cost and scalability. In this paper, we present the first CMOS SPAD with performance comparable or better than that of the best custom SPADs, to date. The SPAD-based design, fully integrated in 180 nm CMOS technology, achieves a peak photon detection probability (PDP) of 55% at 480 nm with a very broad spectrum spanning from near ultraviolet (NUV) to near infrared (NIR) and a normalized dark count rate (DCR) of 0.2 cps/$\mu$m$^2$, both at 6 V of excess bias. Thanks to a dedicated CMOS pixel circuit front-end, an afterpulsing probability of about 0.1% at a dead time of $\sim$3 ns were achieved. We designed three SPADs with a diameter of 25, 50, and 100 $\mu$m to study the impact of size on the timing jitter and to create a scaling law for SPADs. For these SPADs, a single-photon time resolution (SPTR) of 12.1 ps, 16 ps, and 27 ps (FWHM) was achieved at 6 V of excess bias, respectively. The SPADs operate in a wide range of temperatures, from −65 $^{\circ }$C to 40 $^{\circ }$C, reaching a normalized DCR of 1.6 mcps/$\mu$m$^2$ at 6 V of excess bias for the 25 $\mu$m at −65 $^{\circ }$C. The proposed SPADs are ideal for a wide range of applications, including (quantum) LiDAR, super-resolution microscopy, quantum random number generators, quantum key distribution, fluorescence lifetime imaging, time-resolved Raman spectroscopy, to name a few. All these applications can take advantage of the vastly improved performance of our detectors, while enjoying the opportunities of megapixel resolutions promised by the economy of scale that is offered by CMOS technologies.

QUBIC IV: Performance of TES bolometers and readout electronics

Abstract: A prototype version of the Q & U bolometric interferometer for cosmology (QUBIC) underwent a campaign of testing in the laboratory at Astroparticle Physics and Cosmology laboratory in Paris (APC). The detection chain is currently made of 256 NbSi transition edge sensors (TES) cooled to 320 mK. The readout system is a 128:1 time domain multiplexing scheme based on 128 SQUIDs cooled at 1 K that are controlled and amplified by an SiGe application specific integrated circuit at 40 K. We report the performance of this readout chain and the characterization of the TES. The readout system has been functionally tested and characterized in the lab and in QUBIC. The low noise amplifier demonstrated a white noise level of 0.3 nV.Hz^-0.5. Characterizations of the QUBIC detectors and readout electronics includes the measurement of I-V curves, time constant and the noise equivalent power. The QUBIC TES bolometer array has approximately 80% detectors within operational parameters. It demonstrated a thermal decoupling compatible with a phonon noise of about 5.10^-17 W.Hz^-0.5 at 410 mK critical temperature. While still limited by microphonics from the pulse tubes and noise aliasing from readout system, the instrument noise equivalent power is about 2.10^-16 W.Hz^-0.5, enough for the demonstration of bolometric interferometry.

Direct Time-of-Flight Single-Photon Imaging

Abstract: This article provides a tutorial introduction to the direct Time-of-Flight (dToF) signal chain and typical artifacts introduced due to detector and processing electronic limitations. We outline the memory requirements of embedded histograms related to desired precision and detectability, which are often the limiting factor in the array resolution. A survey of integrated CMOS dToF arrays is provided highlighting future prospects to further scaling through process optimization or smart embedded processing.

Silicon Photonic Microring-Based 4 × 112 Gb/s WDM Transmitter With Photocurrent-Based Thermal Control in 28-nm CMOS

Abstract: This work presents a hybrid-integrated 4- $\lambda $ micro-ring modulator-based wavelength-division multiplexed (WDM) optical transmitter (OTX) in the O-band, suitable for co-packaged optics. It supports up to 112 Gb/s per wavelength using high-bandwidth micro-ring modulators (MRMs) together with nonlinear equalization in the driver electronics. A thermal control scheme using MRM photocurrent to sense process and temperature variations is implemented, enabling <0.05 dB TDECQ penalty over 10 °C. This compact photocurrent-based control method significantly reduces the hardware and packaging overhead required for ring-based WDM transceivers. Measurements from a 4- $\lambda $ OTX with 28-nm CMOS electronic IC (EIC) and custom silicon photonic IC (PIC) show the OTX supports 112 Gb/s with <0.7 dB TDECQ across all four channels while dissipating 5.8 pJ/bit in the electronics.

Memristor-based PUF for lightweight cryptographic randomness

Abstract: Physical unclonable functions (PUF) are cryptographic primitives employed to generate true and intrinsic randomness which is critical for cryptographic and secure applications. Thus, the PUF output (response) has properties that can be utilized in building a true random number generator (TRNG) for security applications. The most popular PUF architectures are transistor-based and they focus on exploiting the uncontrollable process variations in conventional CMOS fabrication technology. Recent development in emerging technology such as memristor-based models provides an opportunity to achieve a robust and lightweight PUF architecture. Memristor-based PUF has proven to be more resilient to attacks such as hardware reverse engineering attacks. In this paper, we design a lightweight and low-cost memristor PUF and verify it against cryptographic randomness tests achieving a unique, reliable, irreversible random sequence output. The current research demonstrates the architecture of a low-cost, high endurance Cu/HfO[Formula: see text]Si memristor-based PUF (MR-PUF) which is compatible with advanced CMOS technologies. This paper explores the 15 NIST cryptographic randomness tests that have been applied to our Cu/HfO[Formula: see text]Si MR-PUF. Moreover, security properties such as uniformity, uniqueness, and repeatability of our MR-PUF have been tested in this paper and validated. Additionally, this paper explores the applicability of our MR-PUF on block ciphers to improve the randomness achieved within the encryption process. Our MR-PUF has been used on block ciphers to construct a TRNG cipher block that successfully passed the NIST tests. Additionally, this paper investigated MR-PUF within a new authenticated key exchange and mutual authentication protocol between the head-end system (HES) and smart meters (SM)s in an advanced metering infrastructure (AMI) for smartgrids. The authenticated key exchange protocol utilized within the AMI was verified in this paper to meet the essential security when it comes to randomness by successfully passing the NIST tests without a post-processing algorithm.

CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

Abstract: Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today’s devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as academia have put forward their innovations such as event-driven explicit time-coding, exponential-ratio array, switched RC bandgap reference circuit, etc., to make a trade-off between several performance parameters such as die area, ripple rejection, supply voltage range, and current efficiency. However, current LDO architectures in micro and nanometer complementary metal–oxide–semiconductor (CMOS) technology face some challenges, such as short channel effects, gate leakage, fabrication difficulty, and sensitivity to process variations at nanoscale. This review presents the LDO architectures, optimization techniques, and performance comparisons in different LDO design domains such as digital, analog, and hybrid. In this review, various state-of-the-art circuit topologies, deployed for the betterment of LDO performance and focusing on the specific parameter up-gradation to the overall improvement of the functionality, are framed, which will serve as a comparative study and reference for researchers.

Multi-parametric functional imaging of cell cultures and tissues with a CMOS microelectrode array

Abstract: Electrode-based impedance and electrochemical measurements can provide cell-biology information that is difficult to obtain using optical-microscopy techniques. Such electrical methods are non-invasive, label-free, and continuous, eliminating the need for fluorescence reporters and overcoming optical imaging's throughput/temporal resolution limitations. Nonetheless, electrode-based techniques have not been heavily employed because devices typically contain few electrodes per well, resulting in noisy aggregate readouts. Complementary metal-oxide-semiconductor (CMOS) microelectrode arrays (MEAs) have sometimes been used for electrophysiological measurements with thousands of electrodes per well at sub-cellular pitches, but only basic impedance mappings of cell attachment have been performed outside of electrophysiology. Here, we report on new field-based impedance mapping and electrochemical mapping/patterning techniques to expand CMOS-MEA cell-biology applications. The methods enable accurate measurement of cell attachment, growth/wound healing, cell–cell adhesion, metabolic state, and redox properties with single-cell spatial resolution (20 μm electrode pitch). These measurements allow the quantification of adhesion and metabolic differences of cells expressing oncogenes versus wild-type controls. The multi-parametric, cell-population statistics captured by the chip-scale integrated device opens up new avenues for fully electronic high-throughput live-cell assays for phenotypic screening and drug discovery applications.

A Miniaturized 256-Channel Neural Recording Interface With Area-Efficient Hybrid Integration of Flexible Probes and CMOS Integrated Circuits

Abstract: We report a miniaturized, minimally invasive high-density neural recording interface that occupies only a 1.53 mm ² footprint for hybrid integration of a flexible probe and a 256-channel integrated circuit chip. To achieve such a compact form factor, we developed a custom flip-chip bonding technique using anisotropic conductive film and analog circuit-under-pad in a tiny pitch of 75 μm. To enhance signal-to-noise ratios, we applied a reference-replica topology that can provide the matched input impedance for signal and reference paths in low-noise aimpliers (LNAs). The analog front-end (AFE) consists of LNAs, buffers, programmable gain amplifiers, 10b ADCs, a reference generator, a digital controller, and serial-peripheral interfaces (SPIs). The AFE consumes 51.92 μW from 1.2 V and 1.8 V supplies in an area of 0.0161 mm ² per channel, implemented in a 180 nm CMOS process. The AFE shows > 60 dB mid-band CMRR, 6.32 μV _rms input-referred noise from 0.5 Hz to 10 kHz, and 48 MΩ input impedance at 1 kHz. The fabricated AFE chip was directly flip-chip bonded with a 256-channel flexible polyimide neural probe and assembled in a tiny head-stage PCB. Full functionalities of the fabricated 256-channel interface were validated in both in vitro and in vivo experiments, demonstrating the presented hybrid neural recording interface is suitable for various neuroscience studies in the quest of large scale, miniaturized recording systems.

A 0.31-THz Orbital-Angular-Momentum (OAM) Wave Transceiver in CMOS With Bits-to-OAM Mode Mapping

Abstract: This article reports the first chip-based demonstration (at any frequency) of a transceiver front end that transmits and receives electromagnetic waves with a helical distribution of wavefront phase [namely, orbital angular momentum (OAM)]. The CMOS chip consists of eight 0.31-THz modulator/detector units, with an integrated patch antenna, which are placed in a uniform circular pattern with a diameter of one free-space wavelength. The chip transmits OAM modes that are digitally switched among the $m\,\,=0$ (plane wave), +1 (left-handed), −1 (right-handed), and $(+1)+(-1)$ (superposition) states. The chip is also reconfigurable into a receiver mode that identifies different OAM modes with >10-dB rejection of mismatched modes. The array, driven by only one 310-GHz signal generation path, has a measured EIRP of −4.8 dBm and consumes 154 mW of dc power in the OAM source mode. In the receiver mode, it has a measured conversion loss of $\sim 30$ dB and consumes 166 mW of dc power. Using a low-cost 65-nm bulk CMOS technology, the terahertz (THz)-OAM chip has an area of only 2.1 $\times $ 2.6 mm², which is the smallest among all prior OAM prototypes. The output OAM beam profiles and modes’ orthogonality are experimentally verified. The dynamic mode switching capability of the chip is also verified in the time domain across 1-m distance, and a full-silicon OAM link is demonstrated.