Showing papers on "Comparator applications published in 2012"

An Energy-Efficient 15-Bit Capacitive-Sensor Interface Based on Period Modulation

Abstract: This paper presents an energy-efficient capacitive-sensor interface with a period-modulated output signal. This interface converts the sensor capacitance to a time interval, which can be easily digitized by a simple digital counter. It is based on a relaxation oscillator consisting of an integrator and a comparator. To enable the use of a current-efficient telescopic OTA in the integrator, negative feedback loops are applied to limit the integrator's output swing. To obtain an accurate ratiometric output signal, auto-calibration is applied. This eliminates errors due to comparator delay, thus enabling the use of a low-power comparator. Based on an analysis of the stability of the negative feedback loops, it is shown how the current consumption of the interface can be traded for its ability to handle parasitic capacitors. A prototype fabricated in 0.35 μm standard CMOS technology can handle parasitic capacitors up to five times larger than the sensor capacitance. Experimental results show that it achieves 15-bit resolution and 12-bit linearity within a measurement time of 7.6 ms for sensor capacitances up to 6.8 pF, while consuming only 64 μA from a 3.3 V power supply. Compared to prior work with similar performance, this represents a significant improvement in energy efficiency.

A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator

Abstract: A novel dynamic latched comparator with offset voltage compensation is presented. The proposed comparator uses one phase clock signal for its operation and can drive a larger capacitive load with complementary version of the regenerative output latch stage. As it provides a larger voltage gain up to 22 V/V to the regenerative latch, the input-referred offset voltage of the latch is reduced and metastability is improved. The proposed comparator is designed using 90 nm PTM technology and 1 V power supply voltage. It demonstrates up to 24.6% less offset voltage and 30.0% less sensitivity of delay to decreasing input voltage difference (17 ps/decade) than the conventional double-tail latched comparator at approximately the same area and power consumption. In addition, with a digitally controlled capacitive offset calibration technique, the offset voltage of the proposed comparator is further reduced from 6.03 to 1.10 mV at 1-sigma at the operating clock frequency of 3 GHz, and it consumes 54 μW/GHz after calibration.

Hysteretic inductive switching regulator with power supply compensation

Abstract: A system including is plurality of resistors, a plurality of comparators, and a decoder module. The resistors are connected in series between a supply voltage and a common voltage. A first input of each comparator is connected to a reference voltage. A second input of each comparator is respectively connected to one of a plurality of nodes between the resistors. The decoder module is configured to receive an output from each comparator and to output a plurality of bits based on the output of each comparator. Each of the plurality of bits indicates a different one of a plurality of voltage ranges. A present value of the supply voltage lies in one of the plurality of voltage ranges.

Techniques for measuring voltages in a circuit

Abstract: A circuit can include a comparator, a resistor divider, a control circuit, and a multiplexer. The comparator compares an internal supply voltage of the circuit to a selected reference voltage. The resistor divider generates reference voltages. The control circuit receives an output signal of the comparator and generates a select signal. The multiplexer transmits one of the reference voltages from the resistor divider to the comparator as the selected reference voltage in response to the select signal.

Energy-efficient single-clock-cycle binary comparator

Abstract: A new fast low-power single-clock-cycle binary comparator is presented. High speed is assured by using parallel-prefix architecture, whereas low power is guaranteed by reducing the switching activities of the internal nodes. When implemented with the ST 90 nm 1 V CMOS technology, the proposed circuit exhibits a 4.5 GHz maximum running frequency and 0.77µW/ MHz energy dissipation. Copyright © 2010 John Wiley & Sons, Ltd.

Converter with hysteretic control

Abstract: A hysteretic power converter constituted of: a switched mode power supply; a hysteretic comparator, a first input of the comparator arranged to receive a feedback signal providing a representation of the output voltage of the switched mode power supply and a second input of the comparator arranged to receive a reference voltage; a ramp capacitor coupled to one of the first and second input of the comparator; a current source, a terminal of the current source coupled to the ramp capacitor and arranged to drive current to the ramp capacitor; and a switchable current source, a terminal of the switchable current source coupled to the ramp capacitor, the switchable current source arranged to drive current to the ramp capacitor in a direction opposite the current driven by the current source, wherein the switchable current source is alternately enabled and disabled responsive to the output of the hysteretic comparator.

Buck DC-DC converter with accuracy enhancement

Abstract: A buck switching regulator includes a feedback control circuit including a first gain circuit generating a first feedback signal indicative of the regulated output voltage; a ripple generation circuit generating a ripple signal that is injected to the first feedback signal; and a comparator receiving a first reference signal and the first feedback signal to generate a comparator output signal. The switching regulator further includes an offset compensation circuit including a second gain circuit generating a second feedback signal indicative of the regulated output voltage; and an operational transconductance amplifier (OTA) configured to receive the second feedback signal and the first reference signal and to generate an output signal. The output signal of the OTA is coupled to the comparator to adjust an offset to the comparator so as to cancel the offset at the regulated output voltage due to the injected ripple signal.

High-resolution phase interpolators

Abstract: A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

Schmitt Trigger with Controllable Hysteresis Using Current Conveyors

Abstract: Active elements working in the current or mixed mode are still attractive for the design of analog functional blocks. The current conveyor (CC) was defined already in 1968. This paper deals with hysteresis comparators using second generation current conveyor. The comparator is basically a pulse circuit. In these circuits, the maximum rate of change in the output voltage is required during switching from one state to another. In comparators with operational amplifiers the switching time is given by the slew rate of the operational amplifier used, which is not too high. If a current conveyor is used, the time of switching the comparator gets shorter. The comparator is capable to operate at a higher frequency bands and if it is used, for example, in converters, a higher operating frequency can be reached. The connection of an inverting and a non-inverting comparator with adjustable hysteresis is shown as a practical implementation. Using the AD844, results of experimental measurements are presented that confirm the theoretical assumptions and the results of computer simulation.

A dynamic latched comparator for low supply voltages down to 0.45 V in 65-nm CMOS

Abstract: This paper presents a dynamic latched comparator suitable for applications with very low supply voltage. It adopts a circuit topology with a separated input stage and two cross-coupled pairs (nMOS and pMOS) stages in parallel instead of stacking them on top of each other as previous works. This circuit topology enables fast operation over a wide input common-mode voltage and supply voltage range. This comparator is designed in 65-nm CMOS technology with standard threshold transistors (V T ≈0.4V). Simulation shows that it achieves 5mV sensitivity for a sampling rate of 5GS/s with 1.2V supply voltage, 10mV for 250MS/s with 0.5V supply voltage and 100MS/s with 0.45V supply voltage. The simulated delay time of the proposed comparator is about 30% shorter than the dual-tail dynamic comparator with 0.5V supply voltage and only one third compared to that of the conventional one with 0.6V supply voltage when they are designed to have a similar input referred offset voltage in 65nm CMOS technology.

An offset cancellation technique in a switched-capacitor comparator for SAR ADCs

Abstract: An offset cancellation technique for a SAR (successive approximation register) ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and realized in 0.18 μm CMOS. With the first stage preamplifier offset cancellation and low offset regenerative latching approach, the equivalent offset of the comparator is reduced to < 0.55 mV. By using the pre-amplifying and regenerative latching comparison mode the comparator exhibits low power dissipation. Under a 1.8 V power supply, with a 200 kS/s ADC sampling rate and 3 MHz clock frequency, a 13-bit comparison resolution is reached and less than 0.09 mW power dissipation is consumed. The superiority of this comparator is discussed and proved by the post-simulation and application to a 10 bit 200 kS/s touch screen SAR A/D converter.

Reference cell circuit and variable resistance nonvolatile memory device including the same

Abstract: Included are reference cells each including a variable resistance element which reversibly changes between a predetermined low resistance state LR and a predetermined high resistance state HR according to an application of an electric signal, a comparator which compares resistance values of the reference cells, a pulse generation circuit which generates an electric signal for setting the reference cells to LR or HR, and a control circuit which controls operations where application of the generated electric signal to one of the reference cells corresponding to a comparison result of the comparator and application of a new electric signal generated by the pulse generation circuit to one of the reference cells corresponding to a new comparison result of the comparator are repeated, and then one of the reference cells corresponding to a final comparison result of the comparator is connected to an output terminal.

A 0.5 V high-speed comparator with rail-to-rail input range

Abstract: A 0.5 V high-speed comparator with rail-to-rail input range is presented. Unlike conventional rail-to-rail comparators that use both NMOS and PMOS input devices, the proposed design takes advantage of zero-V t NMOS devices that are available in many CMOS processes tailored for analog and mixed signal applications. Design issues associated with the use of zero-V t devices in comparator circuits are analyzed. Based on a 0.13 μm CMOS technology, the proposed design is compared with recently reported sub 1 V comparators and it shows significant performance improvement by the proposed design.

Susceptibility of CMOS Voltage Comparators to Radio Frequency Interference

Abstract: This paper deals with the susceptibility to RF interference (RFI) of common CMOS voltage comparators. Approximate nonlinear analysis and time-domain computer simulations are carried out to highlight the causes of the false commutations induced by the disturbances superimposed onto the nominal input signals. Through these investigations, it is shown that the response of voltage comparators to RFI depends on the comparator initial state. This effect is also confirmed by the results of measurements carried out on a CMOS voltage comparator embedded in a test chip. Based on this, a new voltage comparator that avoids false commutations induced by high-frequency disturbances is proposed.

A/D converter and solid-state imaging apparatus with offset voltage correction

Abstract: Provided is an A/D converter including an input terminal, a reference signal line for supplying a reference signal which changes temporally, a comparator, a correction capacitor connected to an inverting input terminal of the comparator; and an output circuit which outputs digital data corresponding to an analog signal input to the input terminal. In a first state in which a total voltage of a first analog signal and an offset voltage of the comparator is held in the correction capacitor, a second analog signal input to the input terminal is supplied to a non-inverting input terminal of the comparator, and the second analog signal or the total voltage is changed using the reference signal, thereby outputting, from the output circuit, digital data.

On improving the performance of Traff's comparator

Abstract: In this paper a new current comparator is proposed which offers high speed and high resolution while maintaining low power dissipation. The design improves upon previous Traff current comparator by modifying the given gain stage which leads to up to 83% improvement in delay. Simulation results performed on SPICE using TSMC 0.18µm CMOS technology demonstrate that proposed current comparator has a resolution of ± 10nA and delay of 0.86ns at ± 1µA input current. Performance for lower supply voltages is also reported.

A/D converter and solid-state imaging apparatus

Abstract: Provided is an A/D converter (130, 300, 500, 700) including an input terminal (IN), a reference signal line (171) for supplying a reference signal which changes temporally, a comparator (CMP), a correction capacitor (Coff) connected to an inverting input terminal of the comparator; and an output circuit (330) which outputs digital data corresponding to an analog signal input to the input terminal. In a first state in which a total voltage of a first analog signal and an offset voltage of the comparator is held in the correction capacitor, a second analog signal input to the input terminal is supplied to a non-inverting input terminal of the comparator, and the second analog signal or the total voltage is changed using the reference signal, thereby outputting, from the output circuit, digital data.

Non-Linear-Error Correction in Fractional-N Digital PLL Frequency Synthesizer

Abstract: The present disclosure relates to a frequency synthesizer. The frequency synthesizer includes a phase comparator having first and second input nodes. The first input node receives a reference signal having a reference frequency. A channel control block has an input that receives a channel word and an output coupled to the second input node of the phase comparator. A local oscillator (LO) output node provides an LO signal having an LO frequency based on the reference frequency and the channel word. A feedback back couples the LO output node to the second input node of the phase comparator through the channel control block. A non-linear error correction element is operably coupled on a coupling path extending between the phase comparator and the DCO.

Systems and methods for switched-inductor integrated voltage regulators

Abstract: Power controller includes an output terminal having an output voltage, at least one clock generator to generate a plurality of clock signals and a plurality of hardware phases. Each hardware phase is coupled to the at least one clock generator and the output terminal and includes a comparator. Each hardware phase is configured to receive a corresponding one of the plurality of clock signals and a reference voltage, combine the corresponding clock signal and the reference voltage to produce a reference input, generate a feedback voltage based on the output voltage, compare the reference input and the feedback voltage using the comparator and provide a comparator output to the output terminal, whereby the comparator output determines a duty cycle of the power controller. An integrated circuit including the power controller is also provided.

An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator

Abstract: This paper analyzes a pseudo-differential dynamic comparator with a dynamic pre-amplifier. The transient gain of a dynamic pre-amplifier is derived and applied to equations of the thermal noise and the regeneration time of a comparator. This analysis enhances understanding of the roles of transistor's parameters in pre-amplifier's gain. Based on the calculated gain, two calibration methods are also analyzed. One is calibration of a load capacitance and the other is calibration of a bypass current. The analysis helps designers' estimation for the accuracy of calibration, dead-zone of a comparator with a calibration circuit, and the influence of PVT variation. The analyzed comparator uses 90-nm CMOS technology as an example and each estimation is compared with simulation results.

Power amplifier and power transmission apparatus

Abstract: According to one embodiment, a power amplifier includes a variable passive element and a comparator. The variable passive element is connected directly or indirectly to a first terminal of a switch element and serves to increase or reduce a resonant frequency of the amplifier. The comparator compares a voltage of interest with a reference voltage and outputs a control voltage for the variable passive element based on a difference between the voltage of interest and the reference voltage.

Output buffer of source driver

Abstract: An output buffer of a source driver is disclosed. The output buffer includes a buffer input, a buffer output, a differential input stage, a bias current source, an output stage, a compensation capacitor, and a comparator. The output stage and the comparator are both operated between an analog supply voltage (AVDD) and a half analog supply voltage (HAVDD), or both operated between the half analog supply voltage (HAVDD) and a ground voltage. The comparator compares an input signal with an output signal and outputs a control signal to the bias current source according to the compared result.

Background techniques for comparator calibration

Abstract: A method and a corresponding device for performing a background calibration of a comparator in a circuit having a plurality of stages that are connected in a pipelined fashion to an input signal. A digital value of a residue signal, which is output from a first stage in the plurality of stages to a subsequent stage in the plurality of stages, is calculated. The value of the residue signal is compared to at least one threshold. Based on the comparison, a triggering threshold of a selected comparator in the first stage may be adjusted.

Comparator with transition threshold tracking capability

Abstract: A comparator is provided. The comparator includes a voltage generator, a buffer unit and a threshold control loop. The voltage generator has an output terminal for providing a reference voltage according to a constant current. The buffer unit provides an output signal according to a first input signal and a bias signal. The threshold control loop provides the bias signal to the buffer unit according to a second input signal, so as to regulate a transition threshold of the buffer unit to close to the second input signal. The output signal represents a compare result of the first and second input signals. The buffer unit and the threshold control loop are powered by the reference voltage.

Solid-state imaging apparatus and its driving method

Abstract: A solid-state imaging apparatus has: output lines connected commonly to each column of a plurality of pixels; a reference signal generating circuit for generating a reference signal voltage changing in a ramp shape; a comparator for comparing the reference signal voltage with an analog voltage on the output line; and a counter unit for counting, as a digital value, a period from a start of the comparing of the comparator until an inversion of an output signal of the comparator, wherein the reference signal generating circuit sets the reference signal voltage into an offset voltage, thereafter, an input terminal of the comparator is reset, thereafter, the reference signal generating circuit resets the reference signal voltage from the offset voltage into a initial voltage, and thereafter, the reference signal generating circuit generates the ramp-shaped reference signal voltage from the initial voltage, so that the comparator starts the comparing.

Low-offset comparator using capacitive self-calibration

Abstract: A new high-precision self-calibrated comparator for high resolution converters is presented. It uses a bridged-capacitor array as the calibration digital-to-analog converter (DAC) for high power efficiency and low noise. Post-layout simulations in a 1.8V 0.18µm CMOS show that the comparator achieves a less than 50µV offset for a 14-bit target resolution while consumes only 45µW at the frequency period of 300ns.