Showing papers on "Depletion region published in 1975"

The effect of randomness in the distribution of impurity atoms on FET thresholds

Abstract: Significant regions of the depletion layer of a field effect device may contain only hundreds of dopant atoms. The randomness of the distribution of impurity atoms means that the average doping in the depletion layer varies from place to place in the plane of the surface. The cube approximation introduced by Shockley is adopted and used to divide the channel region of an FET into cubes whose edge is equal to the thickness of the depletion layer. The probability distribution of the threshold voltages of the cubes can then be calculated by using the Poisson distribution of impurity numbers. The conductivity of the array of cubes is treated by a modification of percolation theory. The arrays of importance in the theory of the FET are not very large, containing only tens or hundreds of elements, and the differences between nominally identical arrays is of interest to the average behavior of a large system. Random number experiments are used to develop a quantitative description of the probability of conductivity thresholds in the two-dimensional site problem with a finite number of elements. The finite percolation theory is combined with the cube threshold probability distribution to yield the probability distribution of threshold voltages of a field effect transistor in equilibrium.

The effect of randomness in the distribution of impurity atoms on FET thresholds

Abstract: Significant regions of the depletion layer of a field effect device may contain only hundreds of dopant atoms. The randomness of the distribution of impurity atoms means that the average doping in the depletion layer varies from place to place in the plane of the surface. The cube approximation introduced by Shockley is adopted and used to divide the channel region of an FET into cubes whose edge is equal to the thickness of the depletion layer. The probability distribution of the threshold voltages of the cubes can then be calculated by using the Poisson distribution of impurity numbers. The conductivity of the array of cubes is treated by a modification of percolation theory. The arrays of importance in the theory of the FET are not very large, containing only tens or hundreds of elements, and the differences between nominally identical arrays is of interest to the average behavior of a large system. Random number experiments are used to develop a quantitative description of the probability of conductivity thresholds in the two-dimensional site problem with a finite number of elements. The finite percolation theory is combined with the cube threshold probability distribution to yield the probability distribution of threshold voltages of a field effect transistor in equilibrium.

A simplified model for graded-gap heterojunctions

Abstract: A simplified method for calculating the energy band profiles of graded-gap heterojunctions, based on the generalized model of Oldham and Milnes, is presented. The profiles are derived by superposing an energy band grading function and the electrostatic potential in the heterojunction. The latter is obtained by using the depletion layer approximation as for conventional p-n homojunctions. The energy band profiles of hypothetical p(GaAs)-n(Al0·4Ga0·6As) heterojunctions are calculated using the simplified method. For small grading layer widths, the results are in good agreement with the generalized model. The barrier lowering factor η as a function of the graded layer width l is calculated for such heterojunctions. It is found, for acceptor and donor densities of 1018 and 1016 cm−3 respectively, that the barrier height is reduced from 0·47 eV to zero as l increases from zero (abrupt case) to ≈300 A. The applications of these analyses to practical heterojunctions are discussed.

Modelling weak avalanche multiplication currents in IGFETS and SOS transistors for CAD

Abstract: A model is developed for the substrate current of an IGET operating in saturation. This current results from the impact ionization of the channel current carriers in the high field region adjacent to the drain. Due to the exponential dependency of the impact ionization process on the electric field, an accurate description of the field near the drain is essential. An expression for the field, accounting for the two-dimensional nature of the drain space charge region, is used. The result is a closed form expression for the substrate current. By using an appropriate p-n junction model for the source diffusion, the floating substrate potential in SOS devices is evaluated.

Mean free path of hot electrons at the surface of boron‐doped silicon

Abstract: Electrons can be injected from silicon into silicon dioxide in a metal‐oxide‐semiconductor‐transistor (MOST) structure in which electrons are accelerated in the depletion layer of the channel region in a direction perpendicular to the Si‐SiO2 interface. An analysis of the resulting oxide current as a function of the reverse voltage applied to the source and drain regions is carried out using an extension of a model proposed by Shockley. This leads to an estimate of the mean free path λ of the hot electrons in the silicon. It appears that a heavily doped source and drain, formed by a phosphorus diffusion, or the dislocations generated by this diffusion, have the effect of increasing λ by, presumably, the removal of scattering centers. The largest value of λ observed, λ=135 A, is possibly equal to the value of the mean free path for the generation of high‐energy phonons.

Semiconductor profiling using an optical probe

Abstract: The use of a small spot of light for the detection of semiconductor inhomogeneities, is described. The method employed involves a scanned measurement of the surface photovoltage generated in the surface space charge region of the semiconductor. It is shown that scanned surface photovoltage signals may be used to detect defects in Si using either MOS, Schottky barrier or electrolyte contacts to sense the signal. Furthermore, from a spectral measurement it is possible to monitor the variation of carrier lifetime across the area of the sample. It has proven possible using the technique to detect both gross defects in the Si as well as to measure, on a point by point basis, the reduction in carrier lifetime due to them.

Deep-level controlled lifetime and luminescence efficiency in GaP

Abstract: The influence of deep levels on the minority‐carrier lifetime and relative cathodoluminescent efficiency of undoped GaP has been investigated. Evidence that both these parameters are deep‐level controlled is presented. The dominant center was detected by thermal capture and emission of minority carriers optically injected into the depletion layer of Schottky barriers. This center was found to have a depth of ET−EV=0.75 eV and a hole capture cross section of approximately 4×10−14 cm2.

(GaAl)As‐GaAs heterojunction transistors with high injection efficiency

Abstract: n (GaAl)As‐pGaAs‐nGaAs heterojunction transistors were fabricated by the liquid‐phase epitaxial technique, where two kinds of etchants were used to expose the pGaAs base region. The characteristics of the heterojunction transistors are examined as functions of the injection current density and the temperature. Electrical measurements showed that the transistors have a common emitter current gain β of up to 350. The defect current component in the emitter heterojunction is the recombination current in the depletion region.

C−V analysis of a partially depleted semiconducting channel

Abstract: C−V analysis applied to a depletion layer bordering a semiconducting channel does not provide the true impurity distribution if the space−charge region penetrates to another depletion layer at the other side of the channel, i.e., if the channel is partially depleted. Cases in point are an epitaxial semiconducting channel on a semi−insulating chromium−doped gallium arsenide substrate; an n−channel on a p−substrate; and a heterojunction of a semiconducting epitaxial layer on an insulating substrate with interface states causing depletion.

Thermal carrier generation in charge-coupled devices

Abstract: The build-up of thermally generated carriers in a charge-coupled device shift register is characterized by constructing a model for the generation inside a single shift-register bit. Using the model, theoretical response curves are constructed for two practical modes of operation where the contribution from the generation of carriers can be substantial. Experiments are presented which confirm all aspects of the theoretical response curves, including the presence of an initial period of reduced generation in one of the two modes. Procedures for determining generation parameters directly from observed CCD characteristics are presented and implemented. One generation parameter, the minority carrier lifetime τ, is determined by employing the CCD connected in a gate-controlled diode configuration; two others, the depleted surface generation velocity s 0 , and the general shape of the depletion layer, are determined utilizing a curve fitting procedure. The spatial variation in generation rates is also investigated and found to possess a distribution which is skewed positively and not Gaussian.

Method of manufacturing semiconductor device

Abstract: A method of forming a shallow P-N junction under precise control of its position. An impurity doped layer of the first conductivity type is formed, so that the impurity concentration may become a maximum at substantially the surface of a semiconductor substrate or at an inner part of the semiconductor substrate. Ions of impurities of a second conductivity type, opposite to the first conductivity type, are implanted, so that the impurity concentration may become a maximum greatest at the maximum depletion layer thickness in the semiconductor substrate. The P-N junction finally formed is located within the maximum depletion layer thickness.

Comparison of leakage currents in ion‐implanted and diffused p‐n junctions

Abstract: Phosphorous diffused and arsenic ion‐implanted p‐n junctions have been prepared in 0.5‐ and 2‐Ω cm p‐type 〈100〉 Si wafers. Leakage currents have been measured on gated diode structures of various geometries as a function of bias voltage and temperature. From these measurements the relative importance of the surface, depletion layer, and bulk carrier generation to junction leakage have been determined. The leakage current levels measured on the ion‐implanted junctions are comparable to those measured on the diffused junctions. The surface generation leakage component is the largest, ranging from 5×10−15–10−13 A/mil2 at 25 °C. This sufficiently large to dominate the leakage current for junctions with areas less than approximately 103 mil2. The depletion‐layer generation current IDB is much smaller than would be expected. It is only comparable to the diffusion current at 25 °C where IDB?IDIFF?10−16 A/mil2 for defect‐free junctions. IDIFF becomes the largest for large‐area diodes or for junctions of any area ...

The effect of emitter doping gradient on f T in microwave bipolar transistors

Abstract: The effect of the emitter doping gradient on the transit time in microwave bipolar transistor structures has been investigated. The range of gradients was chosen to cover those typically found in shallow phosphorus- and arsenic-emitter diffusions. The results show that there is appreciable free carrier storage in the emitter space charge layer. The Storage decreases when the doping gradient in the junction is increased. This effect can account for the improved f T values of arsenic emitter transistors. The free carrier storage in the emitter space charge layer is compared with predictions deduced from the theoretical analysis of Morgan and Smits [1].

Transfer gate-less photosensor configuration

Abstract: The charge generated in semiconductor material by incident radiation is transferred to an adjacent region of the semiconductor material by lowering the potential on the adjacent region of semiconductor material relative to the potential in the region where the charge was initially generated. Charge is prevented from flowing back to the region where it was generated by means of a potential barrier formed between the generation region and the adjacent region by a region of semiconductor material highly doped relative to the substrate between said adjacent region and the region in which the charge is generated.

Surface-generation statistics and associated thermal currents in metal-oxide-semiconductor structures

Abstract: The non-steady-state statistics are derived for traps at the silicon-oxide interface of metal-oxide-semiconductor (MOS) structures. These results are applied to derive the surface-generation current ${I}_{g}$ vs. temperature $T$ characteristic associated with the generation of electron-hole pairs through the interfacial traps. It is shown that for a negligible rate of generation of carriers in the depletion layer of the semiconductor, the surface generation ${I}_{g}\ensuremath{-}T$ characteristic reflects the trap distribution in the lower-half of the band gap. Furthermore, it is shown that the $I\ensuremath{-}T$ curves associated with the bulk-generation and the surface-generation processes exhibit characteristics which allow the two processes to be distinguished.

Nonvolatile semiconductor memory

Abstract: A nonvolatile random access memory array comprising variable threshold insulated gate field effect transistor devices is described Each memory element is comprised of a variable threshold field effect gate region located adjacent to a single sensing diffusion which is used to sense change in electrical potential of the sensing diffusion as the effective capacitance of the diffusion is coupled into a depletion region under the gate electrode during a READ cycle Information is written into the memory by selectively applying a field in excess of a critical magnitude across the variable threshold dielectric to cause the device to assume a high or low threshold state To read information out of the memory, an inversion region extending from the sensing diffusion under the gate region is used to effectively switch, or reconfigure, the equivalent electrical circuit of the device to alter the capacitive loading presented by the device to the sensing diffusion depending upon whether the device is in a high or low threshold condition Various gate structures for improving the sensitivity of the memory are disclosed along with a single or multiple pulse sensing scheme which increases sensed voltage and reduces fatigue problems usually associated with conventional variable threshold semiconductor devices

On a variational inequality and its approximation, in the theory of semiconductors*

Abstract: The determination of the space charge layer in p-n junction semiconductors leads to a boundary value problem with unknown interfaces The solution u(x, y) which is the potential at (x, y) satisfies in the domains separated by the interface either the Poisson equation or the Laplace equation We show that this problem reduces to a variational inequality, giving existence and uniqueness of the interfaces and at the same time discuss a direct computational technique based on the finite element method 1 Introduction The devices that are mathematically modeled are based on the p-n junction effect: contact between materials of p type (acceptor of electrons) and of n type (donor of electrons) As a result of the tendency of holes to diffuse into the n region and of electrons into the p region, a nonconducting region is set up along the junction, called a space charge layer A reverse biased potential applied to the junction widens the space charge layer The unknown or free boundaries limiting the space charge region are interfaces with another, conducting region These interfaces are determined by the concentrations of donors and acceptors and the potentials applied We shall consider primarily in this paper the case of the beveled p-n junction (1), (2), which confines the breakdown in the body by making a lower field on the surface The mathematical model of such a case can be described as follows

Temperature dependence of turn-on voltage of gold-doped MOSFETs

Abstract: The temperature dependence of the turn-on voltage of gold-doped and control n- and p-channel MOSFETs has been measured. To account for the large positive shift of turn-on voltage, V T Au , of gold treated n- and p-channel devices, it has been proposed that the gold eliminates the fast interface traps of continuous energy distribution, and that additional acceptor states very close to the valence band can cause additional charge Q A Au , which can dominate the effect of acceptor and donor levels of gold ions in the silicon surface space charge region, and can also over-compensate the surface state charge, Q ss . To fit the theoretical V T Au versus T curve to experimental curves, an accumulation of electrically active gold within the surface space charge region has been considered in n-channel devices and depletion in p-channel devices.

The dynamics of conduction electrons in surface space charge layers

Abstract: After a quick sketch of activities in the area of dc conductivity studies on semiconductor surface space charge layers, the paper presents a comprehensive summary of the high frequency, dynamical studies. We discuss in succession microwave frequency measurements of the parallel conductivity, the far-infrared resonance spectroscopy between electric subbands of the space charge layer and cyclotron resonance. In a concluding section we present some results on photoconductivity experiments and a discussion of some other possible resonance effects.

Semiconductor device having at least one PN junction and channel stopper surrounder by a protecture conducting layer

Abstract: A semiconductor device is disclosed which has a first semiconductor layer of one conductivity type and low impurity concentration, a second semiconductor region of the opposite conductivity type forming a PN junction with the first semiconductor layer, a third semiconductor region of the first mentioned conductivity type formed in the first semiconductor layer which surrounds the PN junction and forms an LH junction with the first semiconductor layer, a passivating layer covering at least the PN and LH junctions, and a conductive layer extending on the passivating layer covering at least the inner periphery of the third region and connected to the first semiconductor layer through an electric barrier layer.

Electrical and Photovoltaic Properties of CdS-GaAs Junctions

Abstract: Heterojunction photodiodes were made by epitaxial growth of CdS on GaAs substrate using the close-spaced technique, and their photoelectric properties were examined as a function of the substrate temperature. Good rectification and photovoltaic properties were obtained on n–n CdS–GaAs junctions. The junction showed Schottky-diode like photoresponse. Since the carrier concentration in the CdS layers was much larger than that in the GaAs substrate, the depletion layer between these junctions extended mainly on the GaAs side. The diffusion of Cd into the GaAs substrate affected photoelectric properties of the diodes. The technical data for the optimum growth conditions for good characteristics are presented. The quantum efficiency of 69% from photon to electron for monochromatic light of 6328 A is obtained.

Shot noise in back biased p-n silicon diodes

Abstract: An earlier calculation of the noise due to generation of carriers in the space charge region in a p-n silicon diode by Lauritzen and by Scott and Strutt is corrected for the fact that the field distribution in the space charge region of a p-n junction is linear instead of uniform. If the noise is expressed as SI(f) = 2eIΓ2, we find Γ 2 = 11 15 in a p+n or n+p junction, instead of Γ 2 = 10 15 found previously.

Current-voltage characteristics of silicon metallic-silicide interfaces

Abstract: The general quantum and electronic theory of the metal-semiconductor contacts, proposed in previous works, is applied to silicon-metallic silicide interfaces in order to calculate their current-voltage characteristics. The analysis takes into account the actual potential profile due both to the semiconductor depletion layer and to the electric dipole created, around the metal-semiconductor interface (MSI), by the quantum mechanical tunneling of the metal free electrons into the semiconductor and by the metal conduction band bending. The current across the MSI, ascribed to the thermionic assisted tunneling, is calculated by taking into account the anisotropy of the effective masses, the many valley-structure of the semiconductor energy bands and the quantum mechanical reflection and tunneling through the energy barrier by means of the generalized transmission probability of Kemble. The results shown by the analysis, which excludes explicity the image-force lowering of the energy barrier height, are the reduction of the height and width of the barrier itself and (hence) the increase of its “transparency” to the thermionic current produced by the increase of the reverse bias voltage and/or of the semiconductor impurity concentration. The effects of such properties of the energy barrier on the current-voltage characteristics of the MSI are the absence of a true reverse saturation current, an ideality factor n greater than 1 and a value of the energy barrier height, deduced from the forward current-voltage characteristics, lower than that true and than that obtained from the measured of the junction capacitance vs the bias voltage. The analysis, applied to interfaces between n -type silicon and the metallic silicides RhSi, ZrSi 2 , PtSi and Pd 2 Si, yields numerical values which agree well with the experimental ones obtained by several authors on the same contacts which, when it is necessary to eliminate field-enhancement at the electrode periphery and leakage currents, incorporate a guard ring. Effectively such a guard ring and the absence of intervening layers of oxide and of other contaminants in the silicon-metal silicide contacts allow one to acquire experimental data more easy to interpret quantitatively than those relative to other contact types.

Low transient effect switching device and method

Abstract: A P-channel MOS double gated transistor is provided with an electrical shield element located between the drain and the second gate. The shield is electrically connected to the first gate and is dc biased by the first gate control voltage at FIRST GATE SELECT. The presence of the first gate control voltage causes all the shield capacitances to charge and causes a depletion region between the shield and the drain. Prior to SECOND GATE SELECT, the electrical transient effects of activating the shield with a dc bias have expired. SECOND GATE SELECT introduces new transients (noise current), noteable charging of the capacitance between the drain and the second gate and formation of the final section of depletion region proximate the second gate completing the P channel. This capacitance is drastically reduced by the intervening shield, and the depletion transient is minimized by the priming depletion region established by the shield voltage.

Two-dimensional analysis of triode-like operation of junction gate FET's

Abstract: Triode-like operation of junction gate FET's is analyzed by two-dimensional computer simulation. Triode-like characteristics are shown to appear with the channel normally off and the depletion layer reaching the drain electrode. Triode-like current arises from carrier injection from the source electrode into the depleted region. Triode-like operation is achieved without intrinsic material.

Tunnel injection of minority carriers in semi-conductors

Abstract: Disclosed are multi-layer thin-film devices having adjacent insulator-semiconductor layers employing n-or-p-type semiconductors wherein a charge maintained at the insulator-semiconductor interface creates a depletion region that substantially suppresses tunneling of majority carriers while enhancing tunneling of minority carriers. When employed in a metal-insulator semiconductor (MIS) device wherein the semiconductor is a compound such as gallium arsenide (GaAs) or Cadmium Sulfide (CdS), such minority carrier injection substantially increases the luminescence efficiency.

Resonant circuit using variable capacitance diode

Abstract: A resonance circuit having an inductor, a capacitor and a semiconductor with a junction, and means for applying a signal to the semiconductor junction. The semiconductor junction satisfies the equation: ##EQU1## where C represents the capacitance of the semiconductor junction when a voltage V is applied thereto and the junction of the semiconductor is reverse biased, C' is a constant, and the inductor and capacitor are connected in series.

Signal processing apparatus

Abstract: Signal processing apparatus wherein acoustic waves are generated and propagated through a piezoelectric semiconductor so as to parametrically interact adjacent to an output electrode so as to provide electric fields which vary the depletion layer adjacent to the output electrode to drive the output circuit.