Showing papers on "Dopant Activation published in 2006"

System for heat treatment of semiconductor device

Abstract: Disclosed is a heat treatment system for semiconductor devices. The heat treatment system is used in a heat treatment process for semiconductor devices, such as a crystallization process for an amorphous silicon thin film or a dopant activation process for a poly-crystalline silicon thin film formed on a surface of a glass substrate of a flat display panel including a liquid crystal display (LCD) or an organic light emitting device (OLED). The heat treatment system transfers a semiconductor device after uniformly preheating the semiconductor device in order to prevent deformation of the semiconductor device during the heat treatment process, rapidly performs the heat treatment process under the high temperature condition by heating the semiconductor device using a lamp heater and induction heat derived from induced electromotive force, and unloads the semiconductor device after uniformly cooling the semiconductor device such that the semiconductor device is prevented from being deformed when the heat treatment process has been finished. The heat treatment system rapidly performs the heat treatment process while preventing deformation of the semiconductor device by gradually heating or cooling the semiconductor device.

Sub-15 nm n+/p-germanium shallow junction formed by PH3 plasma doping and excimer laser annealing

Abstract: An n + /p germanium (Ge) ultrashallow junction formed by PH 3 plasma doping (PLAD) and KrF excimer laser annealing is demonstrated. In order to improve the n-type dopant activation without significant diffusion in the n + /p-Ge junction, we applied laser annealing on the PLAD samples. Compared with rapid thermal annealing (RTA), the laser annealing yielded shallower junction depth (∼15 nm) with low sheet resistance and comparable leakage current characteristics in the Ge n + /p junction. Therefore, PLAD with laser annealing can be considered as an alternative method for fabricating future Ge metal-oxide-semiconductor field-effect-transistors.

Gate electrode dopant activation method for semiconductor manufacturing

Abstract: In one embodiment, the invention generally provides a method for annealing a doped layer deposited on a substrate. The method includes depositing a polycrystalline layer on a substrate surface such as a gate oxide layer and implanting the polycrystalline layer with a dopant to form a doped polycrystalline layer. The method further includes exposing the doped polycrystalline layer to a rapid thermal anneal to readily distribute the dopant throughout the polycrystalline layer. Subsequently, the method includes exposing the doped polycrystalline layer to a laser anneal to activate the dopant in an upper portion of the polycrystalline layer. The laser anneal incorporates the dopant, atoms into the crystalline lattice of the polycrystalline material.

Millisecond Annealing: Past, Present and Future

Abstract: The challenge of achieving maximal dopant activation with minimal diffusion has re-awakened interest in millisecond-duration annealing processes, almost two decades after the initial research in this field. Millisecond annealing with pulsed flash-lamps or scanned energy beams can create very shallow and abrupt junctions with high concentrations of electrically active carriers, but solutions for volume manufacturing must also meet formidable process control requirements and economic metrics. The repeatability and uniformity of the temperature cycle is the key for viable manufacturing technology, and the lessons from the development of commercial rapid thermal processing (RTP) tools are especially relevant. Advances in the process capability require a fuller understanding of the trade-off between dopant activation, defect annealing. diffusion and deactivation phenomena. There is a strong need for a significant expansion of materials science research into the fundamental physical processes that occur at the short time scales and high temperatures provided by millisecond annealing.

Analysis of Dopant Diffusion and Defect Evolution during sub-millisecond Non-melt Laser Annealing based on an Atomistic Kinetic Monte Carlo Approach

Abstract: n-type dopant diffusion during sub-millisecond (ms) non-melt laser annealing (NLA) is investigated through the experiments and atomistic KMC modeling. Laser-only annealing can improve the n-type dopant activation and achieve shallow junctions. KMC model with vacancy complexes indicates that laser-only annealing for nFET can achieve highly activated junctions and reduce dopant fluctuations in the channel region and that P is an attractive replacement for the As extension with laser-only anneal.

Advances in pulsed-laser-deposited AIN thin films for high-temperature capping, device passivation, and piezoelectric-based RF MEMS/NEMS resonator applications

Abstract: In this paper we report recent advances in pulsed-laser-deposited AIN thin films for high-temperature capping of SiC, passivation of SiC-based devices, and fabrication of a piezoelectric MEMS/NEMS resonator on Pt-metallized SiO2/Si. The AlN films grown using the reactive laser ablation technique were found to be highly stoichiometric, dense with an optical band gap of 6.2 eV, and with a surface smoothness of less than 1 nm. A low-temperature buffer-layer approach was used to reduce the lattice and thermal mismatch strains. The dependence of the quality of AlN thin films and its characteristics as a function of processing parameters are discussed. Due to high crystallinity, near-perfect stoichiometry, and high packing density, pulsed-laser-deposited AlN thin films show a tendency to withstand high temperatures up to 1600°C, and which enables it to be used as an anneal capping layer for SiC wafers for removing ion-implantation damage and dopant activation. The laser-deposited AlN thin films show conformal coverage on SiC-based devices and exhibit an electrical break-down strength of 1.66 MV/cm up to 350°C when used as an insulator in Ni/AlN/SiC metal-insulator-semiconductor (MIS) devices. Pulsed laser deposition (PLD) AlN films grown on Pt/SiO2/Si (100) substrates for radio-frequency microelectrical and mechanical systems and nanoelectrical and mechanical systems (MEMS and NEMS) demonstrated resonators having high Q values ranging from 8,000 to 17,000 in the frequency range of 2.5–0.45 MHz. AlN thin films were characterized by x-ray diffraction, Rutherford backscattering spectrometry (in normal and oxygen resonance mode), atomic force microscopy, ultraviolet (UV)-visible spectroscopy, and scanning electron microscopy. Applications exploiting characteristics of high bandgap, high bond strength, excellent piezoelectric characteristics, extremely high chemical inertness, high electrical resistivity, high breakdown strength, and high thermal stability of the pulsed-laser-deposited thin films have been discussed in the context of emerging developments of SiC power devices, for high-temperature electronics, and for radio frequency (RF) MEMS.

Thermal stability of a HfO2∕SiO2 interface

Abstract: Using high-angle annular-dark-field scanning transmission electron microscopy, we showed how annealing at 1000°C changes the chemical composition distribution at a HfO2∕SiO2 interface. The observed change in the distribution was analyzed in terms of Hf diffusion in SiO2; the diffusion coefficient was estimated to be 2.5×10−18cm2∕s. This diffusion coefficient indicates that the high-temperature annealing, such as that in the conventional dopant activation process used to fabricate semiconductor devices, barely changes the chemical composition distribution at the HfO2∕SiO2 interface.

Dopant activation in subamorphized silicon upon laser annealing

Abstract: In this letter, the authors study the dopant activation and dopant distribution in a Si+ subamorphized Si (SAI-Si) when subjected to laser annealing (LA). The results show an enhanced boron activation in the SAI-Si in the nonmelt regime as compared to a crystalline Si (c-Si). The enhancement is caused by a vacancy-rich surface generated by the Si+ preimplantation that promotes the incorporation of boron atoms into the substitutional sites. On the other hand, shallow-melt LA produces a similar boron activation in both SAI-Si and c-Si samples due to a melting that consumes the entire as-implanted profile and the vacancy-rich region.

Defects evolution and dopant activation anomalies in ion implanted silicon

Abstract: The interactions between the defects and the implanted dopants are at the origin of the diffusion and activation anomalies that are among the major obstacles to the realisation of ultra-shallow junctions satisfying the ITRS requirements. In this paper, we present some recent results on the evolution of extended defects in technology relevant conditions for the fabrication of p+/n ultra-shallow junctions and elucidate for each of them the role of the defects in the diffusion and activation anomalies exhibited by the implanted dopants. The presented studies range from the formation of large Boron-Interstitial Clusters in high-fluence B+-implanted silicon, to the deactivation/reactivation of preamorphised ultra-shallow junctions and, finally, to the impact of co-implanted F on the thermal stability of preamorphised junctions.

Low Temperature Dopant Activation for Integrated Electronics Applications

Abstract: A major area of research for integrated electronic systems is the development of systems on glass or plastic. These alternative substrate materials impose significant constraints on electronic device fabrication, including limitations on chemical and thermal processes. This work presents an investigation on the activation of ion-implanted dopants without using the high temperature processes of conventional CMOS. The annealing temperature applied was 600°C, which could potentially enable integrated microelectronics on high-quality glass. Additional factors studied included the annealing technique (furnace or rapid thermal processing), and the use of pre-amorphization implants. Ion-implant modeling along with SIMS and SRP data was used to develop a comprehensive understanding of the experimental results. The performance of transistors fabricated with low-temperature constraints on both bulk silicon and thin-film SOI will be presented.

45nm Node p+ USJ Formation With High Dopant Activation And Low Damage

Abstract: We investigated various p+ extension implantation dopant species (B, BF 2 , B 10 H 14 & B 18 H 22 ) and annealing techniques (spike, flash, laser and SPE) to achieve high dopant activation low damage ultra-shallow junctions (USJ) 15-20nm deep for 45nm node applications. New USJ metrology techniques were investigated to determine: 1) surface dopant activation level and 2) junction quality (residual implant damage) using contact and non-contact full wafer metrology methods. We discovered that using molecular dopant species (B 10 H 14 & B 18 H 22 ) either high temperature (flash or laser) annealing or low temperature SPE annealing are very promising for the 45nm node process integration with SiON or high-k Hf-based dielectric gate stack structures because of their wide temperature range for dopant activation without diffusion.

Crystal Damage Removal by Spike and Flash Annealing

Abstract: The formation of extended defects resulting from the precipitation of the large amounts of interstitials and vacancies generated during the dopant and pre-amorphisation implantation is the major issue related to the formation of highly doped p+/n junctions. Interactions between defects and implanted dopants produce diffusion and activation anomalies that are among the major obstacles to the realisation of ultra- shallow junctions satisfying the ITRS requirements. The ideal thermal treatment should remove all the damage and get a high dopant activation with minimal diffusion. Modifying first the depth of the end-of-range damage by varying the pre- amorphisation implantation energy and the thermal budget by using second (spike) and millisecond (fRTP) annealing, the optimal values for implantation energy and thermal budget can be extracted for a complete defect annihilation. Transmission electron microscopy is used to determine the crystal quality.

Evaluation method of semiconductor device, manufacturing method of the semiconductor device, design management system of device comprising the semiconductor device, dose amount control program for the semiconductor device, computer-readable recording medium recording the program, and dose amount control apparatus

Abstract: There is provided a new method of obtaining the dopant activation rate of a device accurately and simply in a different way from a method of obtaining a carrier density with use of a Hall measurement or CV measurement, and also provided a production method of a device performed with a proper threshold voltage control, that is, a dose amount control, according to the obtained activation rate The inventor devised a method in which the activated dopant density (first dopant density) in a semiconductor film is obtained from the threshold voltage and the flat band voltage of a device, then the dopant activation rate is obtained from the ratio of the obtained activated dopant density to the added dopant density (second dopant density) obtained by SIMS analysis The invention allows easily obtaining the dopant activation rate in the channel region and the impurity region of the device

Low Temperature Dopant Activation for Applications in Thin Film Silicon Devices

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Modeling and Experiments of Boron Diffusion During Sub-Millisecond Non-Melt Laser Annealing in Silicon

Abstract: Boron diffusion and defect evolution during sub-millisecond (ms) laser annealing with partial SPER are investigated using secondary ion mass spectrometry and transmission electron microscopy. Boron diffusivity enhancement in amorphous-Si is observed during partial SPER at 550 °C. It is shown that boron diffusion during the laser annealing process is a 2-step diffusion (SPER + Laser). The depth of the amorphous layer affects the dopant activation behavior. During sub-ms laser annealing, end-of-range defects are formed and show an evolution behavior. {311} defects cannot completely transfer to dislocation loops after 1300 °C laser annealing. It is considered that the thermal budget of sub-ms laser is too small for full defect evolution. Atomistic diffusion modeling using a kinetic Monte Carlo method can explain the defect behavior during laser annealing.

Physical Modeling of Defects, Dopant Activation and Diffusion in Aggressively Scaled Bulk and SOI Devices: Atomistic and Continuum Approaches

Abstract: In this overview we examine how advanced continuum and atomistic modeling can help to understand and resolve process and device design issues for the 65 nm technology generation and beyond. The following implantation-related issues are reviewed: wafer temperature for different types of implant equipment and its impact on defect formation and amorphization, ion scattering off the photoresist mask and its impact on threshold voltage variation, dual rotation halo implant instead of the conventional quad rotation halo implant, and engineering of the source/drain junction overlap for diffusionless annealing by using tilted implants. The following annealing-related issues are also considered: limitations of spike anneal; benefits of cocktail junctions, heat transfer mechanisms for spike and millisecond annealing, and implant damage evolution for different thermal budgets. Taken together, implant, annealing, and layout conditions are shown to explain observed threshold voltage and transistor performance variations. In addition, the effects of transistor geometry on dopant diffusion, activation, and defect formation are shown for several generations of bulk and FDSOI MOSFETs.

High Dopant Activation And Low Damage P+ USJ Formation

Abstract: High dopant activation and low damage p+ ultra‐shallow junctions (USJ) 15–20nm deep for 45nm node applications have been realized using B10H14 & B18H22 implant species along with flash, laser or SPE diffusion‐less activation annealing techniques. New USJ metrology techniques were employed to determine: 1) dopant activation level and 2) junction quality (residual implant damage) using both contact and non‐contact methods.

Modeling and Simulation of the Influence of SOI Structure on Damage Evolution and Ultra-shallow Junction Formed by Ge Preamorphization Implants and Solid Phase Epitaxial Regrowth

Abstract: Preamorphization implant (PAI) prior to dopant implantation, followed by solid phase epitaxial regrowth (SPER) is of great interest due to its ability to form highly-activated ultra-shallow junctions. Coupled with growing interest in the use of silicon-on-insulator (SOI) wafers, modeling and simulating the influence of SOI structure on damage evolution and ultra-shallow junction formation is required. In this work, we use a kinetic Monte Carlo (kMC) simulator to model the different mechanisms involved in the process of ultra-shallow junction formation, including amorphization, recrystallization, defect interaction and evolution, as well as dopant-defect interaction in both bulk silicon and SOI. Simulation results of dopant concentration profiles and dopant activation are in good agreement with experimental data and can provide important insight for optimizing the process in bulk silicon and SOI.

Ultra‐Shallow Junctions Formed By Sub‐Melt Laser Annealing

Abstract: This paper presents an overview of blanket and device wafer studies with sub‐melt laser annealing as the sole dopant activation technique. Blanket wafer studies of the activation and diffusion of n‐ and p‐type junction implants have focused on the influence of the pre‐amorphization depth and laser annealing temperature. In addition, deep sub‐micron NMOS and PMOS transistors with effective gate lengths down to 40 nm have been fabricated. With optimized implant conditions several critical transistor parameters, such as gate/extension overlap and polysilicon dopant depletion, can be improved when sub‐melt laser annealing is used instead of conventional spike anneal.

Activation of arsenic in epitaxial Hg1–xCdxTe (MCT)

Abstract: This paper reviews arsenic (As) dopant activation processes in the various forms of epitaxial MCT. Extrinsic doping of MCT is an important part of MCT technology and As doping is preferred as it is a shallow acceptor dopant with low diffusivity and 100% activation can be achieved under the correct growth and/or post-growth annealing conditions. It is, however, amphoteric so that under Te-rich growth conditions it can be incorporated as a donor (As Hg ) and under metal-rich conditions as an acceptor (As' Te ). For As concentrations up to ~ 2 × 10 18 cm -3 the amphoteric model provides a satisfactory basis for explaining the behavior on annealing layers at temperatures above ~ 250 o C. Under Te-rich conditions in LPE- and MBE-grown layers can be either compensated n-type or the As can be inactive. The quantitative model of Schaake is used to obtain an expression for the activation anneal time in terms of As concentration, layer thickness, composition and temperature. Layers grown by MOVPE can show up to 100% acceptor activation if the stoichiometric conditions during the CdTe growth cycle of the interdiffused multilayer (IMP) process are maintained as metal-rich. In as-grown MBE layers the evidence indicates that As is incorporated in the form of tetramers that can dissociate at higher temperatures. The issue of establishing whether layers are electrically intrinsic at the annealing temperatures used to activate the As acceptor in LPE and MBE layers is also discussed.

Sub-30nm Mosfet Fabrication Technology Incorporating Precise Dopant Profile Design using Diffusion-Less High-Activation Laser Annealing

Abstract: Sub-30nm MOSFET fabrication technology is proposed based on a dedicated process redesign suitable for a non-melt laser annealing technique Two major features of the laser annealing (LA), ie diffusion-less and higher dopant activation enable us to apply more elaborate channel engineering, involving multiple halo implantations and optimized gate-predoping, that contributes further scaling of a functional gate-length (Lg) and effective gate-insulator thickness (Tinv), maintaining sufficient current drivability prior to any local stress engineering applied, for instance, ION = 650/340 [muA/mum] (nMOS/pMOS) at IOFF = 100 nA/mum, Vdd = 09V, were obtained for sub-30nm Lg (and also sidewall length) devices

Impact of Annealing Temperature Ramps on the Electrical Activation of N+ and P+ Co-Implanted SiC Layers

Abstract: We have performed nitrogen and phosphorus co-implants at room temperature to obtain high n-type carrier concentration layers in SiC. An inductive heating RTA furnace has been used for the activation annealing. The influence of the temperature ramp parameters such as rise/decrease temperature speed and intermediate annealing steps on the dopant activation rate and surface morphology have been investigated. A reduction of the temperature ramp slope reduces the surface roughness by 50%. Inclusion of a pre-activation annealing step at low temperatures (1300°C) further reduces the surface roughness. However, the use of slower ramps or an intermediate annealing step during ramp up reduces the free carrier concentration. The faster the ramp up, the higher the activation rate and the resulting doping. We also demonstrate that the inclusion of a postactivation annealing at intermediate temperatures (1150°C) reduces significantly the surface roughness. In addition, the use of this post-annealing treatment does not degrade the activation rate nor the carrier Hall mobility, and activation rates close to 100% have been obtained.

Germanium … The Semiconductor of Tomorrow?

Abstract: Germanium is being investigated as an alternative channel material for mainstream CMOS. Although aspects of processing technology have similarities to silicon, ion implantation, and particularly the activation of dopants and removal of implant damage appear to be fundamentally different. In this paper we review some of the issues and present results that are encouraging in the context of PMOS devices.

Merits of heat assist for melt laser annealing

Abstract: In this paper, the potential for sub-10-nm junction formation of partial-melt laser annealing (PMLA), which is a combination of solid-phase regrowth and heat-assisted laser annealing (HALA), is demonstrated. HALA and PMLA are effective for reducing laser-energy density for dopant activation and for improving heating uniformity of device structure. The absence of melting at the dopant profile tail for PMLA results in a negligibly small diffusion at this region. A high activation rate is achievable by melting the upper part of the amorphous-silicon layer. The obtained sheet resistance of 10-nm-deep junctions was about 700 /spl Omega//sq. for both n/sup +//p and p/sup +//n junctions. These results imply that PMLA is applicable for much shallower junction formation.

Implementation of flash technology for ultra shallow junction formation : Challenges in process integration

Abstract: Several methods for annealing to form ultra shallow junctions are being developed encompassing short bursts of optical energy derived from the discharge of Xe-arc lamps. The flash technology heats the wafer surface to very high temperatures for dopant activation, yet minimizes dopant diffusion which is needed for sub 65nm technologies. A number of challenges remain in implementing the technology for volume fabrication, particularly the control of defect formation and the pattern sensitivity on the wafer surface. The plausible regions of flash energy combined with the assist temperature have been investigated to achieve good activation, yet maintain a low defect level. This has been verified through leakage characteristics of the source/drain extensions. Other aspects of implementation were investigated to formulate a processing sequence which achieves suitable device characteristics. A process integration methodology is described with corresponding device data, electrical and physical, to note improvement...

Nonconventional flash annealing on shallow indium implants in silicon

Abstract: The diffusion behavior and the electrical characteristics of indium doped layers in silicon were studied. Indium was implanted in silicon at energies of 70 and 25 keV to doses of 5.8 and 3×1014, respectively. The implants were performed both in amorphous and crystalline silicon. The implants were submitted to a combination of thermal annealing, RTA, and flash annealing to regrow the implanted layers and activate the dopant. Four point probe sheet resistance measurements and Hall effect measurements were carried out to test the electrical properties of the implanted layers. The atomic concentration profiles were assessed using secondary ion mass spectrometry. A drastic increase in the dopant activation was observed following co-implanting with carbon. Moreover, the carbon presence inhibits the indium diffusion and segregation in damaged areas. The preamorphizing treatment affects the indium diffusion in two ways. For low thermal budget anneals the diffusion is suppressed, conversely the diffusion is enhanc...

Optimization of annealing for ClusterBoron® and ClusterCarbon PMOS SDE

Abstract: High dopant activation and low implant damage are crucial in realizing the formation of a low resistivity ultra shallow junction (USJ). Future annealing process requires diffusion less activation and will ultimately define the junction depth. Conventional boron implant at ultra-low energies perform poorly in throughput and in energy contamination. Molecular species (B18H22) can provide implants with no energy contamination and low beam divergence along with self-amorphization. Implantation of ClusterBoron in combination with ClusterCarbon can provide junction depths in the 15-20 nm regime and achieve a higher level of dopant activation with conventional spike anneal. We used various ClusterBoron and ClusterCarbon energies and doses along with various anneal techniques to arrive at an optimum resistivity and junction depth for PMOS SDE applications. We carried out various analytical measurements like SIMS, sheet-resistance to understand the self-amorphization, enhanced dopant activation and the damage level effect of the dopants after the anneals. The results will be discussed in detail in the paper

Ultra-shallow Junction Formed by Plasma Doping and Laser Annealing

Abstract: We investigated ultra-shallow junction prepared by plasma doping (PLAD) and laser annealing (LA). Although PLAD is promising doping technology for the sub-45nm technology node due to the high dose rate at low energy, it has problems which is related with hydrogen or fluorine. The implanted hydrogen generally increases damage in the Si substrate. The fluorine also retards dopant activation and increases dopant deactivation during post-annealing step. Conventional one step annealing processes such as rapid thermal annealing (RTA) or excimer laser annealing (LA) are not effective method for high dopant activation. To minimize the effect of hydrogen or fluorine, we propose additional pre-annealing followed by conventional laser annealing. By employing low temperature pre-annealing, we can improve electrical characteristics such as low sheet resistance, high activation rates, shallow junction depth and reduced dopant deactivation. The improvement can be explained by reduced defect density and out-diffusion of fluorine or hydrogen which in turn enhances dopant activation during ELA.

Ultrashallow Arsenic n+/p Junction Formed by AsH3 Plasma Doping

Abstract: We have investigated the ultrashallow n+/p junction formed by AsH3 plasma doping (PLAD) and the effect of hydrogen on dopant activation. Since hydrogen balance gas (99% H2) was used for AsH3 PLAD, the incorporation of a significant concentration of hydrogen resulted after PLAD. The incorporated hydrogen caused various problems, such as low dopant activation, high resistance, and high leakage current. These problems were traced to hydrogen-induced damage, which was confirmed by cross-sectional transmission electron microscopy (XTEM). Therefore, pre-annealing at low temperature, which can effectively reduce the undesired hydrogen effects, is a necessary step toward obtaining a high-quality, ultrashallow arsenic n+/p junction via AsH3 PLAD.