Showing papers on "Electronic packaging published in 2009"

Thermal Measurement and Modeling of Multi-Die Packages

Abstract: Thermal measurement and modeling of multi-die packages with vertical (stacked) and lateral arrangement became a hot topic recently in different fields like RAM chip packaging or LEDs and LED assemblies. In our present study, we present results for a more complex structure: an opto-coupler device with four chips in a combined lateral and vertical arrangement. The paper gives an overview of measurement and modeling techniques and results for stacked and multichip module (MCM) structures. It describes actual measurement results along with our structure function-based methodology which helps validating the detailed model of the package being studied. For stack-die packages, we suggest an extension of the DELPHI model topology. Also, we show how one can derive junction-to-pin thermal resistances with a technique using structure functions.

Ultrasonic Bonding for MEMS Sealing and Packaging

Abstract: The feasibility of ultrasonic bonding for hermetic microelectromechanical systems (MEMS) packaging has been demonstrated utilizing the solid phase vibration and welding process to bond two elements rapidly at low temperature. Two different approaches have been developed including lateral and vertical ultrasonic bonding setups with three sets of material bonding systems: In-to-Au, Al-to-Al, and plastics-to-plastics. The process utilizes purely mechanical vibration energy to enable low temperature bonding between similar or dissimilar materials without precleaning of the bonding surfaces. In these prototype demonstrations, the typical bonding process used tens of watts at room temperature environment and the bonds were accomplished within seconds for bonding cavities with areas of a few mm2 . Preliminary tests show that packaged MEMS cavities can survive gross leakage tests by immersing the bonded chip into liquids. As such, ultrasonic bonding could potentially be broadly applied for hermetic MEMS sealing and packaging especially where temperature limitation is a critical issue. Ultrasonic polymeric bonding could be applied for capping polymer-based microfluidic chips. This paper describes the ultrasonic bonding and hermetic sealing processes as well as the characterizations of bonding tools and equipment setups.

Impact of Humidity on Dielectric Charging in RF MEMS Capacitive Switches

Abstract: A novel technique is used to distinguish the charging of the surface from that of the bulk of the dielectrics of different types of RF MEMS capacitive switches under different electric fields and humidity levels. In general, bulk charging dominates in dry air, while surface charging increases linearly with increasing humidity. Under comparable electric fields and humidity levels, switches made of silicon dioxide are less susceptible to surface charging than switches made of silicon nitride. These quantitative results not only underscore the importance of packaging the switches in a dry ambient atmosphere, but also validate the novel technique for evaluating the effectiveness of dielectric preparation and packaging.

Rheology and Thermal Conductivity of Diamond Powder-Filled Liquid Epoxy Encapsulants for Electronic Packaging

Abstract: The traditional silica-based epoxy system used for electronic packaging has a poor thermal conductivity of less than 1 W/mK and no longer meets the increasingly stringent thermal management requirements of many packaging applications. The current commercial availability of low-cost diamond powders with very high-thermal conductivity makes it possible to consider diamond powder-filled epoxy for high-end product packaging. This paper reports the design, rheology, and experimentally determined thermal conductivity results on the multimodal diamond powder-filled epoxy system for liquid encapsulants. Rheology studies of the monomodal diamond powder in epoxy show the necessity of the use of surfactants when the powder sizes are below 10 mum. A high-thermal conductivity of 4.1 W/mK was achieved for epoxy-filled by 68% volume loading of diamond powders, which required a multimodal particle size distribution (nine sizes). Comparative measurements of electronic junction temperatures of Si diodes sealed by the diamond powder-filled epoxy and commercial silica-epoxy show a much better thermal performance of the diamond-filled epoxy, which suggests the potential application of the diamond-filled epoxy for packaging high-end electronic products.

A Cost-Effective MEMS Cavity Packaging Technology for Mass Production

Abstract: Cost effective microelectromechanical system (MEMS) packaging methods have been required, because the cost portion of the MEMS package is more than 80% of the manufacturing cost of a MEMS device. For this reason, cost-effective MEMS packaging is proposed in this paper for mass production using copper (Cu) lead frames (L/F) as a preplated frame (PPF). Package types include an epoxy molding compound (EMC) cavity wall and an on-frame type. The EMC-cavity package consists of a substrate, a cavity wall and a flat lid on top of the cavity. The on-frame package has a folded lid without a cavity wall. Finite element method (FEM) numerical modeling is performed to anticipate the mechanical warpage and stress of the packages. Assembled MEMS cavity packages were tested for wire pulling, lid pulling, hermetic test, and reliability tests in order to prove the feasibility of this packaging. The wire bonding strength was improved by 40% using plasma cleaning before wire bonding. Through a lid pulling test, a lid bonding strength of 2.40 kgf on average was obtained using an epoxy adhesive. Finally, all samples of the packages passed the reliability tests of the TC, HAST, and HTST, standardized by Joint Electron Device Engineering Council (JEDEC). Also, this cavity package showed excellent hermeticity through leak tests.

RF and Microwave Microelectronics Packaging

Abstract: RF and Microwave Microelectronics Packaging presents the latest developments in packaging for high-frequency electronics. It will appeal to practicing engineers in the electronic packaging and high-frequency electronics fields and to academic researchers interested in understanding leading issues in the commercial sector. It covers the latest developments in thermal management, electrical/RF/thermal-mechanical designs and simulations, packaging and processing methods as well as other RF/MW packaging-related fields.

Alternative approach in 3D MEMS-IC integration using fluidic self-assembly techniques

Abstract: Nowadays, industries are investigating new, original and appropriate solutions to address challenges in 3D MEMS-IC large-scale integration. Self-assembly techniques are among those. We report on an alternative approach inspired from fluidic self-assembly and using the flip-chip method. Here, solder bumps are directly formed onto a MEMS chip using liquid solder solution in a bath. The self-alignment process is operated after surface treatment by plasma deposition to form high and low wettability selective patterns. Finally, MEMS and electronic chips are permanently bonded after low thermal heating without any pressure. Electrical contact is established and electromechanisms of the microsystems are proven. Compared to classic MEMS-IC flip-chip methods, this strategy presents many advantages: it is a low-cost and fast fabrication process requiring no specific equipment for deposition of solder bumps. Furthermore, it can be applied on different substrates and it does not require a specific pressure method during the bonding process. This strategy is also an appropriate fabrication method for large-scale MEMS integration where electronic connection density is high.

A Microfluidic Packaging Technique for Lab-on-Chip Applications

Abstract: In this paper, we address the often-neglected challenges of microfluidic packaging for biochemical sensors by proposing an efficient direct-write microfluidic packaging procedure. This low-cost procedure is performed through a programmable dispensing system right after a routine electronic packaging process. In order to prove the concept, the simulation, fabrication and chemical testing results of implemented hybrid system incorporating microelectronics and microfluidics are also presented and discussed.

A Low-Temperature SU-8 Based Wafer-Level Hermetic Packaging for MEMS Devices

Abstract: We have developed a novel all SU-8 packaging method for microelectromechanical system (MEMS) devices. The process is low temperature and low cost and it allows for nonhermetic as well as hermetic packaging. The nonhermetic package can be applied to sensors. The process flow is based on a partial and a full exposure of SU-8 negative resist using two masks. The underexposed region results in cross-linking of only a surface layer, while the underlying resist is not cross-linked and can be removed using SU-8 developer. By depositing a second SU-8 layer a sealed package for MEMS devices can be achieved. The packaging method provides any pattern and cavity clearance since it is solely based on lithography steps. The concept of the packaging method is introduced in this paper and then its practical validity demonstrated using simulation and characterization results.

Optimisation modelling for thermal fatigue reliability of lead‐free interconnects in fine‐pitch flip‐chip packaging

Abstract: Purpose – This paper aims to present an integrated optimisation‐modelling computational approach for virtual prototyping that helps design engineers to improve the reliability and performance of electronic components and systems through design optimisation at the early product development stage. The design methodology is used to identify the optimal design of lead‐free (Sn3.9Ag0.6Cu) solder joints in fine‐pitch copper column bumped flip‐chip electronic packages.Design/methodology/approach – The design methodology is generic and comprises numerical techniques for computational modelling (finite element analysis) coupled with numerical methods for statistical analysis and optimisation. In this study, the integrated optimisation‐modelling design strategy is adopted to prototype virtually a fine‐pitch flip‐chip package at the solder interconnect level, so that the thermal fatigue reliability of the lead‐free solder joints is improved and important design rules to minimise the creep in the solder material, exp...

Reliability and Failure of Electronic Materials and Devices, Second Edition

Abstract: This well-established and well-regarded reference work offers unique, single-source coverage of most major topics related to the performance and failure of materials used in electronic devices and electronics packaging. With a focus on statistically predicting failure and product yields, this book can help the design engineer, manufacturing engineer and quality control engineer all better understand the common mechanisms that lead to electronics materials failures, including dielectric breakdown, hot-electron effects and radiation damage. This new edition will add cutting edge knowledge gained in both research labs and on the manufacturing floor, with new sections on plastics and other new packaging materials, new testing procedures, and new coverage of MEMS devices. Covers all major types of electronics materials degradation and their causes, including dielectric breakdown, hot-electron effects, electrostatic discharge, corrosion, and failure of contacts and solder jointsNew updated sections on "failure physics," on mass transport-induced failure in Cu and low-k dielectrics, and on reliability of lead-free/reduced-lead solder connections.New chapter on testing procedures, sample handling and sample selection, and experimental design.Coverage of new packaging materials, including plastics and composites

Influence of packaging atmospheres on the durability of high-temperature SAW sensors

Abstract: Surface acoustic wave (SAW) devices are a technology of choice for passive, radio-interrogable sensor applications operating under extreme conditions. Suitably designed SAW devices can withstand e.g. temperatures exceeding 400°C. At high temperatures (HT), thermal energies reach values corresponding to the activation energies of reactions between gas components and the crystal's substrate elements and/or the metallisation elements, respectively. Thus, the atmosphere in the hermetic packaging becomes a crucial factor for the SAW device's stability. This work investigates the influence of various potential packaging atmospheres on SAW devices at temperatures up to 650°C. The SAW test structures consist of two delay lines with different lengths, which have been processed with Pt - based thin films. Substrate materials were either langasite (LGS), lithium niobate (LN) or stochiometric lithium niobate (sLN). The devices were annealed in a tube oven equipped with a HT-stable radio frequency (RF) measurement system [1] in different atmospheres at several temperature levels up to 650°C. Afterwards, the SAW surfaces were characterised microscopically.

T/R-module technologies today and possible evolutions

Abstract: After many years of development the active electronically scanned array (AESA) radar technology reached a mature technology level. Many of today's and future radar systems will be equipped with the ASEA technology. T/R-modules are key elements in active phased array antennas for radar and electronic warfare applications. Meanwhile T/R-modules using GaAs MMICs are in mass production with high quantities. Top priority is on continuous improvement of yield figures by optimizing the spread of key performance parameters to come down with cost. To fulfill future demands on power, bandwidth, robustness, weight, multifunctional sensor capability, and overall sensor cost, new emerging semiconductor and packaging technologies have to be implemented for the next generation T/R-modules. Using GaN MMICs as HPAs and also as robust LNAs is a promising approach. Higher integration at the amplitude and phase setting section of the T/R-module is realized with GaAs core chips or even with SiGe multifunction chips. With increasing digital signal processing capability the digital beam forming will get more importance with a high impact on the T/R-modules. For lower production costs but also for sensor integration new packaging concepts are necessary. This includes the transition towards organic packages or the transition from brick style T/R-module to a tile T/R-module.

Ultra-thin chip fabrication for next-generation silicon processes

Abstract: Ultra-thin chip technology is identified as an enabler for overcoming bottlenecks in microelectronics, such as 3D integration, and for leading to new applications, such as hybrid, flexible system-in-foil (SiF). This, however, calls for new techniques in fabricating very thin wafers or chips, in applying them to device integration processes and in assembly and packaging. The application to SiF requires that the ultra-thin chips feature excellent mechanical reliability and flexibility. This paper focuses on a recently introduced novel technology, called Chipfilm™, for fabricating ultra-thin chips. The technology consists of a pre-process Chipfilm™ and a post-process Pick, Crack&Place™. Particular attention is paid to the design and characterization to the mechanical anchors that are broken in the Pick, Crack&Place process to singulate the thin chips. Also discussed is the characterization of the chip's mechanical stability and flexibility.

Development in electronic packaging - moving to 3d system configuration

Abstract: The electronic industry is reducing package dimensions of components as well as complete electronics systems. Surface mount device passives and semiconductor chips have to be mounted together bringing a functional system that must make asked function with necessary reliability and acceptable price. To make up a reliable and cost effective system, the size and weight being reduced by employing lower voltages and higher speeds. For example, the typical size of SMD passives 30 years ago was 1206 when they were first introduced. Generally, all components including electrical joints are becoming miniaturized and smaller. The industry is moving toward a reduced size of 0201 and 01005 for passives, new fine pitch packages for actives, but the PCB now features limits for further integration. System on Package (SOP) is one way to reach the three-dimensional package concept where components will be placed in three-dimensional configuration. A similar concept are "Package on Package" (PoP) or "Package in Package" (PiP).

Silver-Indium Transient Liquid Phase Sintering for High Temperature Die Attachment

Abstract: The demand for electronics capable of operating at temperatures above the traditional 125°C limit continues to increase. Devices based on wide band gap semiconductors have been demonstrated to operate at temperatures up to 500°C, but packaging remains a major hurdle to product development. Recent regulations, such as RoHS and WEEE, increase the complexity of the packaging task as they prohibit the use of certain materials in electronic products such as lead (Pb), which has traditionally been used in high temperature solder die attach. In this investigation, an Ag-In solder paste is presented as a die attach alternative for high temperature applications. The proposed material has been processed by a transient liquid phase sintering method resulting in an in situ alloying of its main constituents. A shift of the melting point of the system, confirmed by differential scanning calorimetry, provided the basis for a breakthrough in the typical processing temperature rule. The mechanical integrity and reliabilit...

Advanced solutions for ultra-thin wafers and packaging

Abstract: DISCO Corporation is a leading manufacturer for equipment and tools for wafer thinning and dicing. “Bringing science to comfortable living by Kiru (Dicing), Kezuru (Grinding) and Migaku (Polishing)” is DISCO's mission. By combining these three core technologies, DISCO provides total solutions to meet the more and more demanding requirements of the Semiconductor industry in terms of manufacturing thin dies with high die-strengths and several new approaches for advanced packaging. When developing such processes, circumstances for the total process flow from front-end to packaging are actively taken into consideration. This article describes various process flows which on the one hand are implemented in the industry as state of the art processes (Conventional process, DBG), but on the other hand also processes which are considered for the future to meet the upcoming requirements for the packaging industry, such as TSV (Through Silicon Via) for die-stacking, thin power devices and the combination of MEMS- and logic devices in one package.

Inspection of through silicon vias (TSV) and other interconnections in IC packages by computed tomography

Abstract: Through silicon vias (TSV) as used in 3D integrated electronic packages were inspected non-destructively by highly resolving nanofocus computed tomography (nanoCT). In particular, in the TSVs plating voids were visualised and quantitatively evaluated by numerical processing of the resulting volumetric data. The nanoCT technology is outlined and further applications such as interposers etc. are considered.

A wafer-scale packaging structure with monolithic microwave integrated circuits and passives embedded in a silicon substrate for multichip modules for radio frequency applications

Abstract: A wafer-level packaging structure with chips and passive components embedded in a silicon substrate for multichip modules (MCM) is proposed for radio frequency (RF) applications. The packaging structure consists of two layers of benzocyclobutene (BCB) films and three layers of metalized films, in which the monolithic microwave ICs (MMICs), thin film resistors, striplines and microstrip lines are integrated. The low resistivity silicon wafer with etched cavities is used as a substrate. The BCB films serve as interlayer dielectrics (ILDs). Wirebonding gold bumps are used as electric interconnections between different layers, which eliminate the need of preparing vias by costly procedures including dry etching, metal sputtering and electroplating. The chemical mechanical planarization (CMP) is used to uncover the gold bumps, and the BCB curing profile is optimized to obtain the appropriate BCB film for CMP process. In this work, the thermal, mechanical, electrical as well as RF properties of the packaging structure are investigated. The packaging thermal resistance can be controlled below 2 °C W−1. The average shear strength of the gold bumps on the BCB surface is about 70 MPa. In addition, a Kelvin test structure is fabricated for resistance testing of the vertical vias. The performances of MMIC and interconnection structure at high frequency are simulated and tested. The testing results reveal that the slight shifting of S-parameter curves of the packaged MMIC indicates perfect transmission characteristics at high frequency. For the transition structure of transmission line, the experimental results are compatible with the simulation results. The insertion loss (S21) is below 0.4 dB from 0 to 40 GHz and the return loss (S11) is less than −20 dB from 0 to 40 GHz. For a low noise amplifier (LNA) chip, the S21 shifting caused by the packaging structure is below 0.5 dB, and S11 is less than −10 dB from 8 GHz to 14 GHz.

Warpage prediction of fine pitch BGA by finite element analysis and shadow moiré technique

Abstract: Warpage is one of the major concerns in manufacturing BGA, CSP, POP or QFN based array packages because a reasonably flat package is critical to successful singulation and board level assembly processes. Warpage of a package is a result of curing shrinkage of encapsulated mold compounds (EMC) and CTE mismatch between various packaging materials. In a completed package, all components are bound together by the crosslinked polymers, i.e. EMC and die-attaching adhesive (D/A). No component can expand or shrink freely. In a typical array package, warpage is in the form of either a ‘crying’ face (corners facing downward) or a ‘smiling’ face (corners facing upward), depending on the correlations of the packaging materials' mechanical, physical and chemical properties. Fine pitch ball grid array (fpBGA) is a chip scale package offering a competitive solution for mobile applications. Package thickness ranges from 1.4mm down to 0.6mm with ball pitches as small as 0.4mm. Since the package is very thin, warpage control is a big challenge. In this study, an accurate finite element model, incorporated appropriate material properties was developed to predict the warpage of fpBGA under reflow condition. The experimental measurements of the warpage behavior of the fpBGA under solder-reflow condition were conducted using an Akrometrix TherMoire PS200. The experimental results were compared with the results of FE analysis, which provides feedbacks for modeling optimization. Effects of material properties and geometric parameters on thermal warpage were then studied using the optimized models.

Modeling transient thermal response of pulsed power electronic packages

Abstract: Steady-state power conversion applications have benefited from numerous packaging and cooling improvements, and there has been a push to apply the same techniques to pulsed power electronic systems and devices. However, the unique aspects of pulsed systems create a trade-off between high package thermal capacity for mitigating rapid temperature rise and low thermal resistance for rapid heat rejection. This report details a numerical study of several electronics packages with varying levels of cooling integration. Using Finite Element equivalent thermal circuit models to perform transient simulations of the packages, the effect of convective improvement and a reduced thermal path upon junction temperature response was examined. Results showed that while a reduced thermal stack and high convection rate speeds the return to steady state after a pulse, the ability for improved convection to mitigate junction temperature rise diminishes significantly as pulse widths approach the thermal time constant of the package. In addition, the reduced thermal capacity of the integrated packages causes them to exhibit higher junction temperature rise and larger temperature swings than basic, non-integrated packages for certain pulse conditions. The worst case examined showed a direct die-cooling package exhibit a 3x increase in peak temperature and a 5x increase in pulse-to-pulse temperature swing over a standard, non-integrated package.

Application of stress sensing test chips to area array packaging

Abstract: Thermal cycling accelerated life testing is often used to qualify area array packages (e.g. Ball Grid Arrays and Flip Chip) for various applications. Finite element life predictions for thermal cycling configurations are challenging due to the complicated temperature/time dependent constitutive relations and failure criteria needed for solders and encapsulants and their interfaces, aging/evolving material behavior (e.g. solders), difficulties in modeling plating finishes, the complicated geometries of typical electronic assemblies, etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling is difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, we really know quite little about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In our research, we are using test chips containing piezoresistive stress sensors to continuously characterize the in-situ die surface stress during long-term thermal cycling of several different area array packaging technologies including plastic ball grid array (PBGA) components, ceramic ball grid array (CBGA) components, and flip chip on laminate assemblies. The utilized (111) silicon test chips are able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The die stresses are initially measured at room temperature after packaging. The assemblies are then subjected to thermal cycling over various temperature ranges including 0 to 100 °C, −40 to 125 °C, and −55 to 125 °C, for up to 3000 thermal cycles. During the thermal cycling, sensor resistances at critical locations on the die device surface (e.g. the die center and die corners) are recorded. From the resistance data, the stresses at each site can be calculated and plotted versus time. The experimental observations show significant cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of thermal cycling duration are also being correlated with the observed delaminations at the die surface (as measured using scanning acoustic microscopy (C-SAM)) and finite element simulations that include material constitutive models that incorporate thermal aging effects.

Packaging and wired interconnections for insertion of miniaturized chips in smart fabrics

Abstract: Electronic devices are currently used in a complete system including mobile phone, television etc… Now, more and more applications need functionality as close as possible to the final system for in situ measurement and control (smart textile, automotive or medical applications) or for security. The components concerned are sensors, light emitting diodes or RFID for example. Concerning microsystem, being integrated in a material means several key properties, including a packaging form adapted to the material manufacturing process, autonomy in terms of energy means for being powered, neutrality versus the initial material properties and resilience, as materials usually get post-processed once manufactured. A particularly attractive support for such integration is the textile way, since textile or textile-like materials are often part of composite materials and are extremely common in the design of complex objects. The "Diabolo" process aims at a direct connection from a chip assembly to external wires without using the traditional bonding / packaging stage. Through a very limited set of wafer scale operations, one or several chip dies can be assembled and connected to conductive wires directly from the chip surface. The result of a fully processed Diabolo assembly is a spool of chips connected to a flexible wire that can be used for incorporation into materials through taping, weaving, knitting, extrusion or more generally inclusion in a liquid phase before curing. The process is still in its early stage of development but our current studies make us confident that assembly throughput as high as 10k UPH (Unit per Hour) can be reached with a relatively simple equipment.

Design, Fabrication, and Calibration of a Piezoresistive Stress Sensor on SOI Wafers for Electronic Packaging Applications

Abstract: This paper presents the development of a piezoresistive stress sensor fabricated on silicon-on-insulator (SOI) wafers for measurement of electronic packaging stress at high temperature. The sensor consists of a series of sensor elements and calibration elements. The sensor elements comprise a 0deg-90deg p-type piezoresistor pair and a plusmn45deg n-type piezoresistor pair for stress measurement, and the calibration elements comprise two polar three-piezoresistor rosettes with specific angels to calibrate the piezoresistive coefficients. The sensor and the calibration piezoresistors are etched from the SOI layer as separate ldquosilicon islandsrdquo on the dielectric buried oxide (BOX) layer. This configuration exploits the excellent electrical insulation of the BOX layer, and enables high-temperature operation of the stress sensor by eliminating the leakage current. Design, fabrication, and the calibration of the piezoresistors at high temperatures show the feasibility of the SOI high-temperature stress sensor. The piezoresistive coefficients are calibrated versus stress and temperature, and the nonlinearity of the resistance versus temperature and the calibration errors are discussed in detail.

Interfacial Fracture Analysis of CMOS Cu/Low- $k$ BEOL Interconnect in Advanced Packaging Structures

Abstract: The increasing use of Cu/low-k dielectrics as multilevel interconnect inclusion materials and aggressive scaling in advanced back-end of line (BEOL) results in a considerable challenge in the structural enhancement of mechanical reliability. Owing to the expected adoption of various ultra dielectrics, the development of a prediction methodology with reliable virtual prototypes is needed before realizing successful integrated circuits (IC) for the next technology node. These prototypes are required to assess the potentiality of interfacial cracks in dissimilar materials, while the impacts of chemical-mechanical polishing (CMP) and packaging are introduced. In order to meet the diversity of a Cu/low-k material system and to resolve the significant size difference between the interconnects and the whole IC device, this research presents finite element (FE) analysis based on the mechanic theory of interfacial fracture integrated with a global/local sub-modeling approach. The unique feature of the proposed novel concept is the adoption of equivalent stacked low-k interconnects within the analysis of a global FE model. Through estimation of the J-integral approach and verification of the four-point bending test (4-PBT), the methodology presented exhibits excellent numerical precision in predicting the cracking energy of low-k packaging. In addition, interfacial fracture parameters and stress fields acting near the crack tip are evaluated using an analytical solution combined with polynomial regressions. The derived results match well compared with the simulated data. Based on the presented demonstrations on the ability of simulated procedures, this investigation provides a desirable manner of understanding the related failure mechanisms of low-k interconnects.

Novel method for crystal defect analysis of laser drilled TSVs

Abstract: Beyond doubt through silicon vias (TSVs) will pave the way for 3D interconnects and therefore initiate what is widely considered as the next revolution for electronic packaging and hetero system integration. During the last years the manufacturing of through silicon vias has been intensely studied in Advanced Packaging and starts industrial commercialization at the moment.

LED and Optical Device Packaging and Materials

Abstract: As for integrated circuit (IC) device packaging, the packaging materials are critical to the LED packaging because the device packaging and assembly yield, and the device reliability and lifetime are determined by the quality of packaging and assembly materials as well as their processing. This presents serious challenges to the development of LED packaging materials, which is exactly the objective of this chapter to review those challenges and to point out the direction of further development.