Showing papers on "Frequency multiplier published in 2009"

Graphene Frequency Multipliers

Abstract: In this letter, the ambipolar transport properties of graphene flakes have been used to fabricate full-wave signal rectifiers and frequency-doubling devices. By correctly biasing an ambipolar graphene field-effect transistor in common-source configuration, a sinusoidal voltage applied to the transistor gate is rectified at the drain electrode. Using this concept, frequency multiplication of a 10-kHz input signal has been experimentally demonstrated. The spectral purity of the 20-kHz output signal is excellent, with more than 90% of the radio-frequency power in the 20-kHz frequency. This high efficiency, combined with the high electron mobility of graphene, makes graphene-based frequency multipliers a very promising option for signal generation at ultrahigh frequencies.

A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$

Abstract: This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N 2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- ?m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 × 0.45 mm2. With a frequency division ratio of 40, the in-band phase noise at 200 kHz offset is measured to be -126 dBc/Hz. The rms PLL output jitter integrated from 10 kHz to 40 MHz is 0.15 ps.

Precise control of broadband frequency chirps using optoelectronic feedback

Abstract: We demonstrate the generation of wideband frequency sweeps using a semiconductor laser in an optoelectronic feedback loop. The rate and shape of the optical frequency sweep is locked to and determined by the frequency of a reference electronic signal, leading to an agile, high coherence swept-frequency source for laser ranging and 3-D imaging applications. Using a reference signal of constant frequency, a transform-limited linear sweep of 100 GHz in 1 ms is achieved, and real-time ranging with a spatial resolution of 1.5 mm is demonstrated. Further, arbitrary frequency sweeps can be achieved by tuning the frequency of the input electronic signal. Broadband quadratic and exponential optical frequency sweeps are demonstrated using this technique.

Real-Time Estimation of Fundamental Frequency and Harmonics for Active Shunt Power Filters in Aircraft Electrical Systems

Abstract: A novel algorithm for fundamental frequency and harmonic components detection is presented in this paper. The technique is based on a real-time implementation of discrete Fourier transform, and it allows fast and accurate estimation of fundamental frequency and harmonics of a distorted signal with variable fundamental frequency. It is suitable for active shunt filter applications, when fast and accurate tracking of the reference signal is required to achieve a good control performance. The main application for the algorithm is aircraft ac power systems, where the fundamental frequency can be either fixed on 400 Hz and its actual value fluctuates around the nominal value, or variable in the range 360-900 Hz. Hence, a real-time estimation of fundamental frequency is essential for active filter control. The proposed algorithm has been at first implemented in Matlab/Simulink for computer simulation, and it has been compared with a Phase Locked Loop (PLL) algorithm for frequency detection and the synchronous dq reference method for harmonic detection. Experimental tests have been carried out in order to validate the simulation results. The distorted current absorbed by a nonlinear load is analyzed and processed by means of a digital implementation of the algorithm running on the active shunt power filter control DSP, in order to calculate the active filter compensating current.

Progress and Challenges Towards Terahertz CMOS Integrated Circuits

Abstract: Key components of systems operating at high millimeter wave and sub-millimeter wave/terahertz frequencies, a 140-GHz fundamental mode voltage controlled oscillator (VCO) in 90-nm CMOS, a 410-GHz push-push VCO with an on-chip patch antenna in 45-nm CMOS, and a 125-GHz Schottky diode frequency doubler, a 50-GHz phase-locked loop with a frequency doubled output at 100 GHz, a 180-GHz Schottky diode detector and a 700-GHz plasma wave detector in 130-nm CMOS are demonstrated. Based on these, and the performance trends of nMOS transistors and Schottky diodes fabricated in CMOS, paths to terahertz CMOS circuits and systems including key challenges that must be addressed are suggested. The terahertz CMOS is a new opportunity for the silicon integrated circuits community.

A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop

Abstract: This paper introduces a pulse injection-locked oscillator (PILO) that provides low jitter clock multiplication of a clean input reference clock. A mostly-digital feedback circuit provides continuous tuning of the oscillator such that its natural frequency is locked to the injected frequency. The proposed system is demonstrated with a prototype consisting of a custom 0.13 mum integrated circuit with active area of 0.4 mm2 and core power of 28.6 mW, along with an FPGA, a discrete DAC and a simple RC filter. Using a low jitter 50 MHz reference input, the PILO prototype generates a 3.2 GHz output with integrated phase noise, reference spur, and estimated deterministic jitter of 130 fs (rms), -63.9 dBc, and 200 fs (peak-to-peak), respectively.

Real-Time Estimation of Power System Frequency Using Nonlinear Least Squares

Abstract: This paper presents a nonlinear least squares method for measuring the power system frequency, wherein the voltage at the measurement point is modeled by using the Fourier series. The estimation of the fundamental frequency is a nonlinear problem in this formulation and is solved by performing a 1-D search over the range of allowed frequency variation. The voltage signal is used for frequency estimation because it is typically less distorted than the line current, resulting in computational efficiency. The robustness of this algorithm with respect to change in various parameters is studied through simulation and the results are validated by hardware implementation using a Virtex IV field-programmable gate array. An application of this algorithm to a shunt active power filter is also presented.

Photonic RF instantaneous frequency measurement system by means of a polarizatio-ndomain interferometer.

Abstract: A new photonic RF instantaneous frequency measurement system is proposed and experimentally demonstrated. A frequency measurement independent of the optical input power and microwave modulation index is achieved by using the constructive and destructive ports of a polarization-domain interferometer. Experimental tests yield a peak-to-peak frequency error lower than 200 MHz for a frequency range of 1-18 GHz.

Integrated circuit comprising frequency generation circuitry for controlling a frequency source

Abstract: An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal

Single-Chip Frequency Multiplier Chains for Millimeter-Wave Signal Generation

Abstract: Two single-chip frequency multiplier chains targeting 118 and 183 GHz output frequencies are presented. The chips are fabricated in a 0.1 ?m GaAs metamorphic high electron-mobility transistor process. The D-band frequency doubler chain covers 110 to 130 GHz with peak output power of 5 dBm. The chip requires 2 dBm input power and consumes only 65 mW of dc power. The signal at the fundamental frequency is suppressed more than 25 dB compared to the desired output signal over the band of interest. The G-band frequency sextupler (×6) chain covers 155 to 195 GHz with 0 dBm peak output power and requires 6.5 dBm input power and 92.5 mW dc power. The input signal to the multiplier chain can be reduced to 4 dBm while the output power drops only by 0.5 dB. The unwanted harmonics are suppressed more than 30 dB compared to the desired signal. An additional 183 GHz power amplifier is presented to be used after the ×6 frequency multiplier chain if higher output power is required. The amplifier delivers 5 dBm output power with a small-signal gain of 9 dB from 155 to 195 GHz. The impedance matching networks are realized using coupled transmission lines which is shown to be a scalable and straightforward structure to use in amplifier design. Microstrip transmission lines are used in all the designs.

A 36–80 GHz High Gain Millimeter-Wave Double-Balanced Active Frequency Doubler in SiGe BiCMOS

Abstract: This letter presents a high conversion gain double-balanced active frequency doubler operating from 36 to 80 GHz. The circuit was fabricated in a 200 GHz fT and fmax 0.18 ?m SiGe BiCMOS process. The frequency doubler achieves a peak conversion gain of 10.2 dB at 66 GHz. The maximum output power is 1.7 dBm at 66 GHz and -3.9 dBm at 80 GHz. The maximum fundamental suppression of 36 dB is observed at 60 GHz and is better than 20 dB from 36 to 80 GHz. The frequency doubler draws 41.6 mA from a nominal 3.3 V supply. The chip area of the active frequency doubler is 640 ?m × 424 ?m (0.272 mm 2) including the pads. To the best of authors' knowledge, this active frequency doubler has demonstrated the highest operating frequency with highest conversion gain and output power among all other silicon-based active frequency doublers reported to date.

Analysis and Design of a CMOS Phase-Tunable Injection-Coupled LC Quadrature VCO (PTIC-QVCO)

Abstract: This paper presents the design, analysis, and characterization of a low-power, low-phase-noise, phase-tunable injection-coupled LC quadrature oscillator (PTIC-QVCO). Two LC VCOs are superharmonically coupled in quadrature phase via a frequency doubler that injects a synchronizing signal at the common source node of the negative transconductor stage. Conceptual and analytical models of the circuit are introduced to derive the conditions for quadrature operation and examine the circuit parameters affecting the phase imbalance due to mismatched VCOs. Additionally, a tunable tail filter (TTF) is incorporated to calibrate the residual quadrature imbalance in presence of a 3-sigma variation in the device parameters and drive the oscillator to its optimum phase noise performance. To validate the proposed approach, measurements have been carried out on a 9 GHz prototype implemented in a 0.18 mum RF CMOS process. With core current consumption of 5 mA at 1.8 V supply voltage, the circuit achieves a measured phase noise figure-of-merit ranging from 177.3 to 182.6 dBc/Hz at 3 MHz offset along the 9.0 to 9.6 GHz frequency tuning range. Quadrature phase correction of plusmn110 at 9 GHz is demonstrated.

A 5-GHz CMOS Frequency Synthesizer With an Injection-Locked Frequency Divider and Differential Switched Capacitors

Abstract: A phase-locked loop (PLL)-based frequency synthesizer at 5 GHz is designed and fabricated in 0.18-mum CMOS technology. The power consumption of the synthesizer is significantly reduced by using an injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. The synthesizer chip consumes 18 mW of power, of which only 3.93 mW is consumed by the voltage-controlled oscillator (VCO) and the ILFD at 1.8-V supply voltage. The VCO has the phase noise of - 104 dBc/Hz at 1-MHz offset and an output tuning range of 740 MHz. The chip size is 1.1 mm times 0.95 mm.

125-GHz Diode Frequency Doubler in 0.13- $\mu{\hbox {m}}$ CMOS

Abstract: The first mm-wave Schottky diode frequency doubler fabricated in CMOS is demonstrated. The doubler built in 130-nm CMOS uses a balanced topology with two shunt Schottky barrier diodes, and exhibits ~ 10-dB conversion loss as well as -1.5-dBm output power at 125 GHz. The input matching is better than -10ndB from 61 to 66 GHz. The rejection of fundamental signal at output is greater than 12 dB for input frequency from 61 to 66nGHz. The doubler can generate signals up to 140 GHz.

A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18- $\mu{\hbox{m}}$ CMOS for $V$ -Band Applications

Abstract: In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the V-band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18-mum CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are -85.2 and -90.9 dBc/Hz, respectively. The reference spur level of -40.16 dBc is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suitable for low-power and high-performance V-band applications.

A wafer-level diamond bonding process to improve power handling capability of submillimeter-wave Schottky diode frequency multipliers

Abstract: We have developed a robust wafer-level substrate bonding process that has allowed us to bond CVD diamond to GaAs membrane-based submillimeter-wave Schottky diode frequency multipliers. The high thermal conductivity of CVD diamond allows the chip to dissipate heat more efficiently thus increasing the power handling capability of the chips. This process has resulted in single-chip multiplier devices working in the submillimeter-wave range that can handle hundreds of milliwatts of input power. Output powers of 40 mW at 250 GHz and 27 mW at 300 GHz from a single chip have been demonstrated with this method. It is expected that by power combining these chips it is now possible to achieve a wideband 300 GHz signal with more than 100 mW of power. This represents a dramatic improvement in the current state of the art and allows one to begin realizing submillimeter-wave radar applications.

Optical Millimeter-Wave Up-Conversion Employing Frequency Quadrupling Without Optical Filtering

Abstract: This study presents two optical frequency quadrupling techniques for generating high-purity millimeter-wave signals with optical carrier suppression. To our best knowledge, this investigation demonstrates for the first time that a frequency quadrupling system requires only a single integrated Mach-Zehnder modulator without an optical narrowband filter to remove undesired optical sidebands. Since no optical filter is needed, fast frequency tuning is straightforward and this approach is particularly attractive for the optical up-conversion in the wavelength-division-multiplexing radio-over-fiber systems. This study provides both theoretical analysis and experimental demonstration. The generated optical millimeter-wave signals are of very high quality with optical carrier and undesired harmonic distortion suppression ratio of more than 36 dB.

A deep-UV optical frequency comb at 205 nm

Abstract: By frequency quadrupling a picosecond pulse train from a Ti:sapphire laser at 820 nm we generate a frequency comb at 205 nm with nearly bandwidth-limited pulses. The nonlinear frequency conversion is accomplished by two successive frequency doubling stages that take place in resonant cavities that are matched to the pulse repetition rate of 82 MHz. This allows for an overall efficiency of 4.5 % and produces an output power of up to 70 mW for a few minutes and 25 mW with continuous operation for hours. Such a deep UV frequency comb may be employed for direct frequency comb spectroscopy in cases where it is less efficient to convert to these short wavelengths with continuous wave lasers.

Multiple frequency antenna array for use with an RF transmitter or receiver

Abstract: A multiple frequency antenna array includes a first antenna circuit and a second antenna circuit. The first antenna circuit has a first radiation pattern and is tuned to a first carrier frequency. The first antenna circuit transmits a first representation of a radio frequency (RF) signal at the first carrier frequency, where the first carrier frequency corresponds to a carrier frequency of the RF signal and a first frequency offset. The second antenna circuit has a second radiation pattern and is tuned to a second carrier frequency. The second antenna circuit transmits a second representation of the RF signal at the second carrier frequency, where the second carrier frequency corresponds to the carrier frequency of the RF signal and a second frequency offset.

Method and circuit for frequency offset estimation in frequency domain in the orthogonal frequency division multiplexing baseband receiver for ieee 802.11a/g wireless lan standard

Abstract: A method for frequency offset estimation in frequency domain is provided. The method comprises the following steps. First, a phase angle of a signal field of the input signal after processed by Fast Fourier Transformation (FFT) and channel equalization is calculated. A frequency offset error originated from at least one frequency offset estimation process in time domain is then estimated according to the phase angle.

Phase-Locked Loop

Abstract: A loop filter for receiving an input signal indicative of a phase-difference between a reference signal and a signal output by a signal generator and forming a control signal for controlling the signal generator in dependence thereon, the loop filter comprising a plurality of filter components that determine the frequency response of the filter, said filter components being arranged so that a first set of said components determines one or more zeros of the filter's frequency response and a second set of said components determines one or more poles of the filter's frequency response, each of said first and second sets of filter components being independent of the other such that the zero(s) and pole(s) of the filter's frequency response may be selected independently

Device and method for expanding frequency band, device and method for encoding, device and method for decoding, and program

Abstract: Disclosed are a device and a method for expanding a frequency band, a device and a method for encoding, a device and a method for decoding, and a program whereby a frequency band is expanded in order to enable a music signal to be reproduced with high sound quality. Band-pass filters (13) obtain multiple subbands from an input signal. A frequency envelope extraction circuit (14) extracts a frequency envelope from the multiple subband signals obtained by the multiple band-pass filters. A high-frequency signal generation circuit (15) generates a high-frequency signal element based on the frequency envelope obtained by the frequency envelope extraction circuit (14) and the multiple subband signals obtained by the band-pass filters (13). A frequency band expander (10) expands the frequency band of the input signal using the high-frequency signal element generated by the high-frequency signal generation circuit (15). The invention can be applied to a frequency band expander, an encoder, and a decoder, for example.

A 300 GHz active frequency-doubler and integrated resistive mixer MMIC

Abstract: An active frequency-doubler MMIC achieving an output frequency of 300GHz and its monolithic integration with a 300GHz resistive mixer is presented. The frequency-doubler provides a broadband source with an average output power of −9.5 dBm and better than 10 % conversion efficiency in the frequency range from 250 to 310 GHz. At 300 GHz, a non-saturated output power of −6.4 dBm is measured at an input power of 1dBm. A 300GHz down-conversion mixer MMIC, combining the frequency-doubler with a resistive mixer, achieves a conversion loss of 20 dB in the RF range from 246 to 300 GHz. Both MMICs are realized in a metamorphic HEMT technology with 50 nm gate-length.

Millimeter wave marine frequency modulation multichannel anti-collision radar

Abstract: The invention relates to the radio-positioning technical field, particularly a millimeter-wave marine frequency modulation multi-channel anti-collision radar, which is realized through the following steps: adopting the full-phase parameters to receive/transmit reference signals; asynchronously controlling the time division and the time sequence; watching the targets which are prone to collision on the water surface in an omni-directional manner through DSP cyclic scanning wave beams by a quasi-optical dielectric lens antenna circular array; controlling the time division SAW multi-channel passive frequency modulation through a plurality of water surface waterway cameras, an own ship speed sensor, a satellite positioning sensor GPS data MCU; sending to antenna array to transmit through an up-converter, T/R3, a frequency multiplier and a power amplifier, a circulator and T/R2; extracting the SAW multi-channel signals from the returning wave through the antenna array, a wave beam switch, T/R1, the circulator, a high amplifier, a down-converter and a medium amplifier; detecting a plurality of barrier target DSPs so as to confirm the position, the distance and the relative speed; displaying the three-dimensional image on a CRT, wherein the closer the ship gets to the target, the higher the resolution power is; controlling the false-alarm identification and tracing the nearest targets; giving an alarm when the distance is smaller than the safety distance; and intelligently avoiding the barriers or reducing if the distance is close to a risk distance, wherein the control is determined based on the actual condition of the water surface environment combined with the own ship speed and the GPS data, thereby improving the shipping safety.

A $K$ -Band CMOS Distributed Doubler With Current-Reuse Technique

Abstract: A K-band distributed frequency doubler is developed in 0.18 mum CMOS technology. This doubler combines the distributed topology for broadband characteristics and current-reuse technique to improve the conversion gain. The high-pass drain line and high-pass inter-stage matching network are used to obtain a good fundamental rejection. A measured conversion gain of better than -12.3 -dB is obtained, and the fundamental rejection is better than 30 dB for the output frequency between 18 and 26 GHz. The dc power consumption is 10.5 mW with a chip size of 0.55 times 0.5 mm2.

Systems and methods for implementing a harmonic rejection mixer

Abstract: Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics.

A spin-wave frequency doubler by domain wall oscillation

Abstract: We present a new mechanism for spin-wave excitation using a pinned domain wall which is forced to oscillate at its eigenfrequency and radiates spin waves. The domain wall acts as a frequency doubler, as the excited spin waves have twice the frequency of the domain wall oscillation. The investigations have been carried out using micromagnetic simulations and enable the determination of the main characteristics of the excited spin-waves such as frequency, wavelength, and velocity. This behavior is understood by the oscillation in the perpendicular magnetization which shows two anti-nodes oscillating out of phase with respect to each other.

A K-Band CMOS Quadrature Frequency Tripler Using Sub-Harmonic Mixer

Abstract: A low-power frequency tripler is designed by using the sub-harmonic mixer configuration for K-band applications. The proposed circuit features quadrature signal generation, applicable to LO signal synthesis in millimeter-wave wireless transceivers. It achieves conversion gain of -5.7 dB at the output frequency of 21 GHz. Implemented in a 0.18 mum CMOS technology, the circuit consumes power of 7.5 mW with 1.5 V supply voltage. The entire die occupies an area of 1000times1050 mum2.

A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS

Abstract: An 8-phase phase-aligned ring oscillator in 90 nm digital CMOS is presented that operates up to 2 GHz. The low-complexity circuit consumes 13 mW at 2 GHz and 1.2 mW at 400 MHz, while a flat in-band phase noise below -120 dBc/Hz is achieved, in close agreement with the presented theory. The circuit occupies an area of 0.008 mm2 .

Design of 24-GHz 0.8-V 1.51-mW Coupling Current-Mode Injection-Locked Frequency Divider With Wide Locking Range

Abstract: A 0.8-V CMOS coupling current-mode injection-locked frequency divider (CCMILFD) with 19.5% locking range and a current-injection current-mode logic (CICML) frequency divider have been designed and fabricated using 0.13-mum 1p8m CMOS technology. In the proposed CCMILFD, the current-mode technique to minimize the loss of input signals and the coupling circuit to enlarge the phase response have been designed to increase the locking range. The locking range of the fabricated CCMILFD is 4.1 GHz with a power consumption of 1.51 mW from a power supply of 0.8 V. In the proposed CICML frequency divider, the current-injection interface is applied to the current inputs to make the circuit operated at a higher frequency with low power consumption under a low voltage supply. The operation frequency of the fabricated CICML frequency divider can divide the frequency range from CCMILFD and consume 1.89 mW from a 0.8-V voltage supply. The chip core areas of the CCMILFD and CICML frequency divider without pads are 0.23 and 0.015 mm2, respectively. The proposed circuits can be operated in a low supply voltage with the advantages of a wider locking range, a higher operation frequency, and lower power consumption.