Showing papers on "Ground bounce published in 2005"

Electromagnetic bandgap power/ground planes for wideband suppression of ground bounce noise and radiated emission in high-speed circuits

Abstract: A power/ground planes design for efficiently eliminating the ground bounce noise (GBN) in high-speed digital circuits is proposed by using low-period coplanar electromagnetic bandgap (LPC-EBG) structure. Keeping solid for the ground plane and designing an LPC-EBG pattern on the power plane, the proposed structure omnidirectionally behaves highly efficiently in suppression of GBN (over 50 dB) within the broad-band frequency range (over 4 GHz). In addition, the proposed designs suppress radiated emission (or electromagnetic interference) caused by the GBN within the stopband. These extinctive behaviors of low radiation and broad-band suppression of the GBN is demonstrated numerically and experimentally. Good agreements are seen. The impact of the LPC-EBG power plane on the signal integrity for the signals referring to the power plane is investigated. Two possible solutions, differential signals and an embedded LPC-EBG power plane concept, are suggested and discussed to reduce the impact.

Split-channel antifuse array architecture

Abstract: Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor. More specifically, the present invention provides an effective method for utilizing split channel MOS structures as an anti-fuse cell suitable for OTP memories.

A novel power plane with super-wideband elimination of ground bounce noise on high speed circuits

Abstract: A novel L-bridged electromagnetic bandgap (EBG) power/ground planes is proposed with super-wideband suppression of the ground bounce noise (GBN) from 600Mz to 4.6GHz. The L-shaped bridge design on the EBG power plane not only broadens the stopband bandwidth, but also can increase the mutual coupling between the adjacent EBG cells by significantly decreasing the gap between the cells. It is found the small gap design can prevent from the severe degradation of the signal quality for the high-speed signal referring to the perforated EBG power plane. The excellent GBN suppression performance with keeping reasonably good signal integrity for the proposed structure is validated both experimentally and numerically. Good agreement is seen.

Digital ground bounce reduction by supply current shaping and clock frequency Modulation

Abstract: In a synchronous clock-distribution network, digital circuits switch simultaneously on the clock edge; therefore, they generate ground bounce due to sharp peaks of the supply current. We demonstrate an effective combination of two methodologies for ground-bounce reduction based on shaping the supply current: 1) introducing intentional skews to the synchronous clock network and 2) frequency modulation of the system clock. The former technique reduces the time-domain peaks as well as the spectral power of the supply current by spreading the simultaneous switching activities. The latter technique reduces the power contained in the clock harmonics by spreading this power into the side lobes formed around the clock harmonics without any change in the spectral power of the supply current. We also describe an analytical framework to analyze the impact of cycle-to-cycle variations of the supply current on the ground-bounce voltage. Simulation results for a 40K-gates circuit in a 0.18-/spl mu/m 1.8-V CMOS process on a bulk-type substrate show around 26 dB reduction in the spectral peaks of the ground-bounce spectrum at the circuit resonance and factors of 3.04/spl times/ and 2.64/spl times/ reduction in the peak-to-peak and RMS values, respectively, of the ground bounce in the time domain when these two techniques are combined. These two techniques are believed to be good candidates for the development of digital low-noise designs in CMOS technologies.

Optimization for the Locations of Decoupling Capacitors in Suppressing the Ground Bounce by Genetic Algorithm

Abstract: In the high-speed digital printed circuit board, decoupling capacitors play an important role in lowering the power-ground planes impedance leading to the ground bounce noise in I/O ports while the logic is in transition. This paper investigates the optimal placement of decoupling capacitors in suppressing the input and transfer impedances of power-ground planes. The cavity model combines with genetic algorithm (GA) here to find the design specification and the optimal placement of the decoupling capacitors.

3D Simulation study of gate coupling and gate cross-interference in advanced floating gate non-volatile memories

Abstract: In this paper we present a 3D simulation study of gate coupling and gate cross-interference in advanced floating gate non-volatile memories. First, the simulation methodology is introduced and validated against experimental data. Then, physical effects that significantly impact the coupling calculation are pointed out. Finally, the method is applied to a sensitivity study of both gate coupling and gate cross-interference in different non-volatile memory architectures showing the increasing importance of this kind of analysis in designing more advanced technologies.

Designing method for high-frequency transistor and high-frequency transistor having multi-finger gate

Abstract: The present invention provides a designing method for a high-frequency transistor, which includes a transistor section, a drain region, and a gate electrode, a source wiring line, a drain wiring line, and a gate wiring line, for optimizing wiring lines and contacts from voltage supplying nodes to electrode lead nodes. The method includes the steps of measuring a sensitivity to a high-frequency characteristic of the high-frequency transistor regarding coupling capacities between the wiring lines and coupling capacities between the wiring lines and the semiconductor substrate from among equivalent circuit parameters which vary in response to a configuration of the wiring lines and the contacts; deciding layered levels individually of the gate wiring line, source wiring line, and drain wiring line based on the measured sensitivities; and designing patterns of the gate wiring line, source wiring line, and drain wiring line in the individually decided layered levels and the positions and the sizes of the wiring lines and the contacts for connecting the wiring lines and the transistor section to each other.

I/O circuitry for reducing ground bounce and VCC sag in integrated circuit devices

Abstract: Methods and circuitry for reducing ground bounce and VCC sag effects in integrated circuit ('IC') devices is provided. In particular, a via-programmable design for I/O circuitry in IC devices is provided. The via-programmable I/O circuitry is used to disconnect I/O pin driver circuitry from and create a substantially direct connection between unused I/O pins and the ground and/or VCC signals of an IC device to reduce ground bounce and VCC sag, respectively.

High-density low-power data retention power gating with double-gate devices

Abstract: A new power gating structure with robust data retention capability using only one single double-gate device to provide both power gating switch and virtual supply/ground diode clamp functions. The scheme reduces the transistor count, area, and capacitance of the power gating structure, thus improving circuit performance, power, and leakage. The scheme is compared with the conventional power gating structure via mixed-mode physics-based two-dimensional numerical simulations. Analysis of virtual supply/ground bounce for the proposed scheme is also presented.

Integrated power switching circuit

Abstract: A power switching circuit includes a power MOS transistor that has a maximum source-drain voltage substantially higher than a permissible gate-source voltage, and that has a current path connected in series with a load between first and second supply terminals, and comprising a gate driver circuit that drives the gate of the power MOS transistor directly from the supply voltage. A gate driver circuit has a pair of series-connected switching transistors connected between the first and second supply terminals. An interconnection node between the switching transistors is connected to the gate of the power MOS transistor. The gate driver circuit further includes a reference voltage source and a voltage comparator comparing the gate voltage of the power MOS transistor with the reference voltage to provide a disabling output that disables one of the switching transistors when the gate voltage of the power MOS transistor reaches the reference voltage. By selecting a reference voltage level not higher than the maximum permissible gate-to-source voltage of the power MOS transistor, its gate is effectively protected from excessive gate-to-source voltage. Yet, the switching transistor in the gate driver circuit other than that connected to the ground supply terminal (usually referred to as Vcc terminal), may have its current path connected directly, or through just a feedback resistor, to the high supply terminal (usually referred to as Vcc terminal).

IR drop and ground bounce awareness timing model

Abstract: As the IC technology scales down, the effect of IR drop/ground bounce becomes increasingly significant. IR drop and ground bounce can compromise the gate driving capability and degrade the IC performance, and even can make IC functional failures. Hence, it is crucial to capture this effect efficiently and accurately in order to improve circuit reliability. In this paper, we proposed a timing model with consideration of IR drop and ground bounce. Our model can be derived directly from the existing timing tables (e.g. Synopsys.db or CLF tables), which are used in normal timing analysis. Compared with the traditional k-factor approach, our method does not require SPICE netlist and SPICE simulations. Moreover, the accuracy of our model is better than k-factor approach.

Progress in the Research of Ground Bounce Removal for Landmine Detection with Ground Penetrating Radar

Abstract: Downward looking ground penetrating radar (GPR) has been considered a viable technology for landmine detection. For such a GPR with the antennas positioned very close to the ground surface, the reflections from the ground surface, i.e., the ground bounce, are very strong and can completely dominate the weak returns from shallowly buried plastic mines. Hence, one of the key challenges of using GPRs for landmine detection is to remove the ground bounce as completely as possible without altering the landmine return. In this paper, we first review existing ground bounce removal algorithms. Then two newly devised adaptive ground bounce removal algorithms, ASaS (Adaptive Shifted and Scaled algorithm) and RLP (Robust Linear Prediction) will be presented. Both ASaS and RLP are based on a flexible data model applicable to rough ground surface and an effective generalized likelihood ratio (GLR) based non-homogeneous detector is devised to further improve their performance. Experimental results show that the proposed algorithms are more robust than conventional ground bounce removal algorithms.

Method and system for amplifying a signal

Abstract: According to one embodiment of the invention, an amplifier includes a gate bias circuit operable to generate a gate bias voltage and a common gate amplifier that includes a transistor having a gate biased by an output of the gate bias circuit and also having a source connected to an inductor for providing a path to ground for direct current flowing through the transistor. According to another embodiment of the invention, a method for amplifying a signal by an amplifier includes generating a gate bias voltage indicative of a difference between a reference voltage and an output voltage of the amplifier, biasing the gate of the common-gate amplifier with the gate bias voltage, and blocking, by a passive device, alternating current signals from flowing from the source of the transistor to ground.

A low noise output buffer capable of operating at high speeds

Abstract: Output buffers which operate at high speeds require delicate handling of the noise on the supply lines. This necessitates control be exercised over current slew rate not only on the rising edge of current but also on the falling edge of the current. A circuit provides control over the current slew rate on the falling edge in high speed output driver charging/discharging heavy load without affecting the speed of the driver (which otherwise would have created supply/ground bounce due to parasitics present in the bonding wires, package pins and on-chip metal interconnects in the I/O ring). The control circuit further suppresses the supply/ground noise by a very significant level while incurring small penalty in terms of silicon area and power dissipation. This circuit includes a CMOS circuit that is cross-coupled input connected to the output buffer input signals with a dummy capacitance coupled to the CMOS circuit output.

Power plane system of high-speed digital circuit for suppressing ground bounce noise

Abstract: The invention relates to a power plane system for suppressing ground bounce noise. The power plane system of the invention comprises a substrate, a power layer and a ground layer. The power layer comprises a plurality of metal units. There is a distance between two adjacent metal units. A plurality of bridges is used for connecting the metal units. The ground layer has a grounding metal plate. According to the invention, when the ground bounce noise occurs, the metal units can broaden the stop-band bandwidth. Therefore, the signals in the stop-band hardly are transmitted so as to suppress the ground bounce noise, and the high frequency ground bounce noise and the electromagnetic radiation can be suppressed efficiently.

A method and apparatus for minimising the influence of a digital sub-circuit on at least partially digital circuits

Abstract: The present relates to a digital sub-circuit suitable for embedding in an at least partially digital circuit for minimising the influence of another digital sub-circuit on the at least partially digital circuit, the other digital sub-circuit being part of the at least partially digital circuit The influence of the other digital sub-circuit may for example be the introduction of ground bounce by switching of the other digital sub-circuit The present invention furthermore relates to an at least partially digital circuit comprising such a digital sub-circuit for minimising the influence of another digital sub-circuit to the at least partially digital circuit and to a method for reducing the influence of another digital sub-circuit to an at least partially digital circuit

Independent gate skewed logic in double-gate SOI technology

Abstract: Independent gate control of double gate SOI devices (D. Fried, 2003 and L. Mathew, 2004) can be effectively exploited to improve performance and reduce power in sub-50nm circuits. In this paper, we have proposed a skewed logic style using independent gate operation of double gate SOI devices.

On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits

Abstract: Switching digital circuits produce current peaks which result in voltage fluctuations on the power supply lines due to the inductive behavior of on-chip and chip-to-package interconnects. A design technique is described in this paper to lower ground bounce in noise sensitive circuits. An on-chip noise-free ground is added to divert ground noise from the sensitive nodes. An on-chip decoupling capacitor tuned in resonance with the parasitic inductance of the interconnects provide an additional low impedance ground path. Ground bounce reductions of about 68% and 22% are demonstrated for a single frequency and random noise, respectively. The noise reduction is shown to depend linearly on the physical separation between the noisy and noise sensitive blocks. The dependence of ground noise on the impedance of the low noise ground is also discussed. The proposed technique exhibits a strong tolerance to capacitance variations. The efficiency of the noise reduction technique drops by several per cent for a plusmn10% variation in the magnitude of the decoupling capacitor. The proposed technique is shown to be effective for both single frequency and random voltage fluctuations on the ground terminal

Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance

Abstract: The paper reports a novel simulation methodology for the analysis and prediction of substrate noise impact on analog/RF circuits taking into account the role of the parasitic resistance of the on-chip interconnect in the impact mechanism. This methodology allows investigation of the role of the separate devices (also parasitic devices) in the analog/RF circuit in the overall impact. In this way, it is revealed which devices have to be taken care of (shielding, topology change) to protect the circuit against substrate noise. The developed methodology is used to analyze the impact of substrate noise on a 3 GHz LC-tank voltage controlled oscillator (VCO) designed in a high-ohmic 0.18 /spl mu/m 1 PM6 CMOS technology. For this VCO (in the investigated frequency range from DC to 15 MHz) impact is mainly caused by resistive coupling of noise from the substrate to the non-ideal on-chip ground interconnect, resulting in analog ground bounce and frequency modulation. Hence, the presented test-case reveals the important role of the on-chip interconnect in the phenomenon of substrate noise impact.

On-Chip Power NoiseReduction Techniques in High PerformanceSoC-Based Integrated Circuits

Abstract: Switching digital circuits produce current peaks whichresult involtage fluctuations onthepowersupply lines duetotheinductive behavior ofon-chip andchip-to-package interconnects. A design technique isdescribed inthispaper tolowerground bounceinnoise sensitive circuits. An on- chipnoise-free ground isaddedtodivert ground noise from thesensitive nodes. Anon-chip decoupling capacitor tunedin resonance withtheparasitic inductance oftheinterconnects provides anadditional lowimpedance groundpath. Ground bouncereductions ofabout68%and22% aredemonstrated forasingle frequency andrandomnoise, respectively. Thenoise reduction isshowntodepend linearly onthephysical separation between thenoisy andnoise sensitive blocks. Thedependence of groundnoise ontheimpedance ofthelownoise ground isalso discussed. Theproposed technique exhibits astrong tolerance tocapaci- tance variations. Theefficiency ofthenoise reduction technique drops byseveral percentfora+10%variation inthemagnitude ofthedecoupling capacitor. Theproposed technique isshown tobeeffective forbothsingle frequency andrandomvoltage fluctuations ontheground terminal. Index Terms-Powerdistribution systems, power noise, ground bounce, decoupling capacitors, RLCimpedances

A theoretical investigation of the resonance damping performance of magnetic material coating in power/ground plane structures

Abstract: Power bus structure, consisting of two parallel solid power and ground planes separated by an insulator, behaves as a cavity resonator at high frequencies. Noise on the power bus, due to a sudden change in the current drawn by an active component, can appear as an undesired spatial fluctuation in the voltage between power and ground, especially at resonant frequencies of the resultant cavity, which may lead to problems in signal integrity, excessive delays, false switching, and radiated emission. These resonances can be suppressed by introducing high-frequency loss into the structure. This paper investigates a simple method to reduce self-/transfer impedance of power/ground planes for mitigating power/ground bounce in high-speed printed circuit board design by adding a thin layer of magnetic material coating to the inside-facing surfaces of copper power and ground plates to increase their effective high-frequency surface impedance. The increased surface impedance will increase the attenuation constant of the propagating wave inside the cavity that benefits reduction of cavity's quality factor (Q factor). The simulation results obtained from a modified cavity resonator model show that increasing surface impedance can dramatically reduce self- and transfer impedances at board resonant frequencies.

Circuit modeling of power/ground plane structures for printed circuit boards

Abstract: With the increase of operating frequency and circuit-component density, signal/power integrity issues due to ground bounces become more important for high-speed digital systems. This paper presents a modal analysis resulting in a multiport equivalent circuit model for the power/ground plane structures in printed circuit boards including effects of dielectric, conductor, and radiation losses. Numerical results represented in Z-parameters verified by the measured data are shown to validate the proposed approach. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 47: 97–99, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21092

Ground bounce calculation due to simultaneous switching in deep sub-micron integrated circuits

Abstract: Supply and ground variation due to switching noise is an important issue in digital and mixed-mode integrated circuits. An approach for calculating the supply and ground bounce is presented in which the effects of parasitic elements of package and bond wires are considered. The proposed method leads to a system of linear equations whose analytical solution can be used to predict the behavior of supply and ground variations. SPICE simulations are used to verify the accuracy of the approach. The importance of modeling package parasitics and the dependence of switching noise on parasitic elements are also discussed.

A new method to achieve improved accuracy with IBIS models

Abstract: IBIS (input/output buffer information specification) models are known to lack information regarding power and ground bounce resulting in incorrect simulations. In this paper, a novel solution to the problem is proposed making it possible to simulate IBIS models with available simulators and have a realistic chance at simulating simultaneous switching noise (SSN) that are present in most if not all high speed circuits. To demonstrate the solution, a CMOS voltage-mode driver circuit and a current-mode LVDS driver circuit are simulated using HSPICE and compared with equivalent circuits created with IBIS models of the same drivers. The IBIS models are created using the s2ibis tool from North Carolina State University.

Power and Substrate Noise Tolerance of Configurable Embedded Memories in SoC

Abstract: When subject to various power and substrate noise, configurable embedded memories in multimedia SoCs are importantly affected with pattern-dependant soft failures. This work investigates the effects of such failures on memory cells, arrays and circuit design. The ground bounce reduces the memory cell current more than the supply voltage drop or the substrate bias dip. A noise track-and-filter (NTAF) architecture, which is a self-timed architecture with specific layout patterns, is presented to provide the required timing relaxation, while minimizing the speed degradation. This NTAF method provides greater noise tolerance and design for manufacturing (DFM) capability. Configurable embedded SRAM and ROM in 0.18 μ m CMOS process are studied.

Modeling and Characterization of High Frequency Effects in ULSI Interconnects

Abstract: This paper discusses the accurate modeling of resistance R, inductance L and capacitance C in sub-100nm process node and their impacts on high frequency effects such as delay, crosstalk, and power/ground bounce. Models of interconnect (wire) resistances increase due to electron scattering at the surface and grain boundaries, and coupling capacitance of high aspect ratio interconnects for sub100nm process nodes are presented. It is observed from test chip measurement that the skin effect and inductive effects of Cu interconnect at high frequencies exhibit different behaviors compared to Al interconnect, presumably because of the presence of CMP dummy metal fills. It is shown that the incorporation of frequency dependent R and L is essential in the modeling and characterization of high frequency effects for high speed ULSI circuits.

Design of a high speed digital interface for multi-standard mobile transceiver RFIC's in 0.13 /spl mu/m CMOS

Abstract: This paper presents the design of two different digital interfaces, both based on current signalling. First the requirements for a digital interface at the baseband output of a multi-standard mobile phone RF front-end are explained. The paper gives an insight of the popular digital interfaces and presents a new concept which is more robust against the ground bounce effect. At the end measurement results of a realized test chip are shown.

Optimal Interconnect ATPG Under a Ground-Bounce Constraint

Abstract: In order to prevent ground bounce, Automatic Test Pattern Generation (ATPG) algorithms for wire interconnects have recently been extended with the capability to restrict the maximal Hamming distance between any two consecutive test patterns to a user-defined integer, referred to as the Simultaneously-Switching Outputs Limit (SSOL). The conventional approach to meet this SSOL constraint is to insert additional test patterns between consecutive test patterns if their Hamming distance is too large; this approach often leads to substantially more test patterns than strictly necessary. This paper presents an algorithm that generates, for a user-defined number of interconnect wires, a minimal set of test patterns that respects a user-defined SSOL constraint. Experimental results show that, in comparison to the conventional approach, our algorithm leads to a significant reduction of up to 60% in the test pattern count and corresponding test application time.

Non-volatile semiconductor storage device and the manufacturing method thereof

Abstract: High integration and making a non-volatile semiconductor memory efficient have been promoted. The memory cell consists of a floating gate, a control gate constituting a word line WL and a MOS transistor having an assist gate. The thickness of the gate oxide film of the assist gate is thinner than the thickness of the gate oxide layer of the floating gate, and the dimensions of the assist gate (gate width) in the direction lying along the word line WL is smaller than the gate length of the floating gate in the direction lying along the word line WL. Moreover, the channel dopant concentration underneath the assist gate is lower than the channel dopant concentration underneath the floating gate.

Leakage power management with NDR isolation devices

Abstract: A method and system for minimizing sub-threshold leakage in a logic block is disclosed. An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device raises the voltage at the virtual ground node above an isolation voltage, which causes NDR isolation device isolates the virtual ground node from ground. The virtual ground control device can then raise the voltage at the virtual ground node to the positive supply voltage to eliminate sub-threshold leakage currents the logic block. Alternatively, the virtual ground control device can raise the voltage at the virtual ground node to the positive supply voltage minus a retention voltage so that storage elements in the logic block can retain state information while still greatly reducing sub-threshold leakage current.