Showing papers on "p–n junction published in 2000"

Current injection emission from a transparent p–n junction composed of p-SrCu2O2/n-ZnO

Abstract: An ultraviolet light-emitting diode (LED) operating at room temperature was realized using a p–n heterojunction composed of transparent conductive oxides, p-SrCu2O2 and n-ZnO. Multilayered films prepared by a pulsed-laser deposition technique were processed by conventional photolithography with the aid of reactive ion etching to fabricate the LED device. A rather sharp emission band centered at 382 nm was generated when a forward bias voltage exceeding the turn-on voltage of 3 V was applied to the junction. The emission may be attributed to a transition associated with the electron–hole plasma of ZnO.

Enhancement mode AlGaN/GaN HFET with selectively grown pn junction gate

Abstract: A report is presented into the fabrication and characterisation of an enhancement mode AlGaN/GaN heterojunction field-effect transistor (HFET) with selectivity grown pn junction gate. At zero gate bias the device channel is depleted due to the high built-in potential of the gate-channel junction. The selective area growth approach enables both depletion and enhancement mode HFETs to be fabricated on the same wafer thus opening up the possibility of designing high speed, low consumption GaN-based logical integrated circuits.

Power semiconductor component

Abstract: The invention relates to a symmetrically blocking power semiconductor component, for example an IGBT, in which a zone (11) of the second conductivity type is formed between the pn junction for forward blocking, which is formed by a first base region (1) of the first conductivity type and a second base region (3) of a second conductivity type, and a pn junction for reverse blocking which is formed on a chip edge of the first base region (1) and a marginal region (30) of the second conductivity type. Said zone (11) of the second conductivity type is doped so weakly that all free charge carriers are removed therefrom already at a low voltage. The inventive power semiconductor component allows emission of the electrical field in both directions of blocking in the same area of the chip surface.

Phase modulator for semiconductor waveguide

Abstract: An optical phase modulator comprises a semiconductor rib wave guide having P and N doped regions forming a PN junction along the path of the rib with terminals for applying a reverse bias to the junction to extend a carrier depletion zone to alter the refractive index, the PN junction is offset from the central axis of the rib but on application of the reverse bias the depletion zone extends over a central axis of the waveguide.

Design of porous silicon antireflection coatings for silicon solar cells

Abstract: A porous silicon (PS) layer formed electrochemically in the outer part of the n emitter of p-n Si junctions can be used as an efficient antireflection coating (ARC). A two-step procedure is presented which can determine the electrochemical parameters leading to the formation of an optimized single-layer PS ARC. Single-layer PS ARCs achieving: 7% effective reflectance between 400 and 1000 nm are obtained on shallow p‐n junction solar cells. To reduce the reflectance further, the design of double-layer ARCs based on PS is investigated. PS layers with different porosities can be realized in a single experiment by modulating the current density during the electrochemical process. It is shown theoretically and experimentally that such PS structures can lead to an effective reflectance below 3%. © 2000 Elsevier Science S.A. All rights reserved.

Annealing of ultrashallow p+/n junction by 248 nm excimer laser and rapid thermal processing with different preamorphization depths

Abstract: Ultrashallow p+/n junctions formed by B+-ion implantation and annealed by spike rapid thermal annealing (RTA) or laser annealing were studied. The effect of the preamorphizing depth on the redistribution of boron atoms after annealing has also been investigated. Our results show that for ultrashallow junctions formed by ultra-low-energy ion implantation and spike RTA, the depth of the preamorphizing implant has very little impact on the junction depth. By optimizing the laser fluence and preamorphization depth, a highly activated, ultrashallow, and abrupt junction can be obtained using a 248 nm excimer laser. The secondary-ion-mass spectrometry results clearly indicate that a step-like profile with a junction depth of 370 A (for a B+ implant at 1 keV) can be formed with a single-pulse laser irradiation at 0.5 J/cm2.

Electroluminescence of a cubic GaN/GaAs (001) p-n junction

Abstract: A cubic GaN p–n diode has been grown on n-type GaAs (001) substrates by plasma assisted molecular epitaxy. For p- and n-type doping, elemental Mg and Si beams have been used, respectively. The optical properties are characterized by photoluminescence at room temperature and 2 K. Current–voltage and capacitance–voltage measurements of the cubic GaN n+–p junction are performed at room temperature. The electroluminescence at 300 K is measured through a semitransparent Au contact. A peak emission at 3.2 eV with a full width at half maximum as narrow as 150 meV is observed, indicating that near-band edge transitions are the dominating recombination processes in our device. A linear increase of the electroluminescence intensity with increasing current density is measured.

pn-junction delineation in Si devices using scanning capacitance spectroscopy

Abstract: The scanning capacitance microscope (SCM) is a carrier-sensitive imaging tool based upon the well-known scanning-probe microscope (SPM). As reported in Edwards et al. [Appl. Phys. Lett. 72, 698 (1998)], scanning capacitance spectroscopy (SCS) is a new data-taking method employing an SCM. SCS produces a two-dimensional map of the electrical pn junctions in a Si device and also provides an estimate of the depletion width. In this article, we report a series of microelectronics applications of SCS in which we image submicron transistors, Si bipolar transistors, and shallow-trench isolation structures. We describe two failure-analysis applications involving submicron transistors and shallow-trench isolation. We show a process-development application in which SCS provides microscopic evidence of the physical origins of the narrow-emitter effect in Si bipolar transistors. We image the depletion width in a Si bipolar transistor to explain an electric field-induced hot-carrier reliability failure. We show two sample geometries that can be used to examine different device properties.

Semiconductor device having ultra-sharp P-N junction and method of manufacturing the same

Abstract: A semiconductor device such as a P-N or P-I-N junction diode, includes a first semiconductor layer having a first conductivity-type and being mounted over a metal address line, and a second semiconductor layer having a second conductivity-type and being mounted over the first semiconductor material. The diode preferably has a thickness of substantially no more than about 1 micron, and the diode includes a P-N junction confined to a thickness of less than about 0.1 micron. In the preferred embodiment the method comprises depositing a first semiconductor layer having a first conductivity type, depositing a second intrinsic layer, annealing to convert both layers to a polycrystalline layer, implanting ions of a second conductivity type into the second layer, and annealing to convert the second layer to a polycrystalline. The result is a diode having an ultra-sharp p-n junction.

Imaging of a silicon pn junction under applied bias with scanning capacitance microscopy and Kelvin probe force microscopy

Abstract: Scanning capacitance microscopy (SCM) and Kelvin probe force microscopy (KPFM) are used to image the electrical structure of a silicon pn junction under applied bias. With SCM, the carrier density inside a diode is imaged directly. With KPFM, the surface potential distribution of an operating diode is measured, revealing different behavior from that in bulk. The surface potential drop is extended deep into the lightly p-doped region at reverse bias, reflecting the existence of the surface space-charge region as confirmed by the numerical simulation.

UV-emitting diode composed of transparent oxide semiconductors: p-SrCu2O2/n-ZnO

Abstract: A UV-emitting diode composed of a hetero-SrCu/sub 2/O/sub 2//ZnO pn junction was fabricated by pulsed laser deposition (PLD). On injecting an electrical current through a pn heterojunction of p-SrCu/sub 2/O/sub 2//n-ZnO, an emission peak centred at 387 nm was observed, originating from excitons or the electron hole plasma in ZnO.

Light emitting semiconductor method and device

Abstract: Silver electrode metallization in light emitting devices is subject to electrochemical migration in the presence of moisture and an electric field. Electrochemical migration of the silver metallization to the pn junction of the device results in an alternate shunt path across the junction, which degrades efficiency of the device. In accordance with a form of this invention, a migration barrier is provided for preventing migration of metal from at least one of the electrodes onto the surface of the semiconductor layer with which the electrode is in contact.

SOI-structure MIS field-effect transistor and method of manufacturing the same

Abstract: A SOI-structure MOS field-effect transistor. In this transistor, agate electrode and a p − region that is a body region are placed into electrical contact by a PN junction portion. An n + -type portion of the PN junction portion is in electrical contact with the gate electrode and a p + -type portion of the PN junction portion is in electrical contact with a p − region. When a positive voltage is applied to the gate electrode, the above configuration ensures that a reverse voltage is applied to the PN junction portion, so that only a small current on the order of the reverse leakage current of the PN junction flows along the path from the gate electrode, to the PN junction portion and the body region, and into the source region.

Imaging the variation in band bending across a silicon pn junction surface using spectromicroscopy

Abstract: We present a characterization of lateral silicon pn junction arrays fabricated on a Si(001) surface using a synchrotron-based scanning photoelectron microscope (SPEM). The Si 2p images show energy dependent contrast which varies continuously across the space charge region between regions of different doping. Combined with measurements of the changes in the Si 2p spectra across the pn junction, we demonstrate the capacity of SPEM in imaging variations in dopant concentration, the width of the charge depletion zone, and variations in band bending with oxide preparation.

SOI-structure MIS field-effect transistor with gate contacting body region

Abstract: A SOI-structure MOS field-effect transistor. In this transistor, a gate electrode and a p− region that is a body region are placed into electrical contact by a PN junction portion. An n+-type portion of the PN junction portion is in electrical contact with the gate electrode and a p+-type portion of the PN junction portion is in electrical contact with a p− region. When a positive voltage is applied to the gate electrode, the above configuration ensures that a reverse voltage is applied to the PN junction portion, so that only a small current on the order of the reverse leakage current of the PN junction flows along the path from the gate electrode, to the PN junction portion and the body region, and into the source region.

Junction profiles of sub keV ion implantation for deep sub-quarter micron devices

Abstract: Ultra shallow junctions <500 /spl Aring/ with steep profiles <8 nm/decade are required for device technologies /spl les/0.13 /spl mu/m as outlined by the recent ITRS Roadmap. For a p/sup +//n junction such profiles can be obtained using sub-keV B ion implantation since both the projected range and more importantly the transient enhanced diffusion are significantly reduced at lower energies. State-of-the-art high current implanters utilize a deceleration mode typically for sub 1 keV implantation in order to increase the beam current and production wafer throughput. Such a mode contains a very low level of energy contamination. This level is measured for sub keV B implants in the Quantum Leap and factors affecting the level of contamination are studied. Spike and soak annealing reduces the effect of the energy contamination on junction profile and depth. The effect of energy contamination on device performance such as L/sub eff/, VT and I/sub DSAT/ is simulated using ISE TCAD.

GaN PN junction issues and developments

Abstract: Critical nitride-based p-n junction issues relating to wide bandgap bipolar device performance include minority carrier lifetime, defect related current characteristics and ohmic contact properties. Recent developments in p-GaN deposition processes resulted in GaN p-i-n UV photodetectors with improved deep UV responsivity, visible light rejection and shunt resistance characteristics. From the device data, the electron diffusion length in p-GaN doped at 1·1018 cm−3 was estimated to be 790 A, and the minority carrier lifetime in the p-GaN was estimated to be 24 ps to 0.24 ns. Improved junction electrical characteristics were achieved using MBE deposition on GaN buffers grown by MOCVD. NiAu ohmic contacts were also made to p-GaN with specific contact resistances less than 10−4 Ω·cm2.

High voltage SiC diodes with small recovery time

Abstract: 4H-SiC diodes with 6 kV blocking capability, low forward voltage drop (4.2 V at 100 A/cm2, 5.8 V at 500 A/cm2), and very small recovery time (≤ 7 ns) have been demonstrated for the first time. Experimental results can be explained by the combination of high lifetime across the major part of the base and the presence near the metallurgical boundary of the p+n junction of a thin layer with a very small carrier lifetime.

`Classical' current-voltage characteristics of 4H-SiC p+-n junction diodes

Abstract: Forward current-voltage characteristics of 4H-SiC p+-n diodes with 5.5 kV voltage-blocking capacity have been studied in the temperature range 297-640?K. `Classical' characteristics, described as a sum of the recombination current in the space charge region and the diffusion current in the base, have been observed for the first time at low current densities over the whole temperature range. Using data on the saturation diffusion current, the hole lifetime in the base is estimated to be about 10-9?s. This value is three orders of magnitude shorter than the hole lifetime measured in the same structures at high injection level. The possible reasons for such a discrepancy are discussed.

Method for fabricating an emitter-base junction for a gallium nitride bipolar transistor

Abstract: The present invention comprises methods for producing semiconductor devices useful in high temperature applications. The invention is based on using silicon ion implantation to convert a portion of the p-type base layer of magnesium-doped GaN into n-type GaN. The boundary of the n-type GaN within the p-type layer then becomes an n-p diode junction which can function as the emitter-base junction. The present methods utilize ion implantation to convert a portion of the p-type layer to n-type thereby forming an n-p junction having desirable diode characteristics. The invention also includes BJT and HBT devices incorporating the present implanted n-p diode junctions.

Method of manufacturing a trench gate field effect semiconductor device

Abstract: A semiconductor body (1) is provided having a first semiconductor region (3) of one conductivity type separated from a first major surface (5 a) by a second semiconductor region (5) of the opposite conductivity type. A trench (7) is etched through the second semiconductor region (5) to an etch stop layer (4) provided in the region of the pn junction between the first (3) and second (5) regions, by using an etching process which enables the etching process to be stopped at the etch stop layer. A gate (8, 9) is provided within the trench (7). A source (12) separated from the first region (3) by the second region (5) is formed adjacent the trench so that a conduction channel area (50) of the second region (5) adjacent the trench provides a conduction path between the source and first regions which is controllable by the gate.

Super-halo formation in FETs

Abstract: A semiconductor substrate has at least one PN junction with dopant atoms at the junction. A non-dopant at the junction provides interstitial traps to prevent diffusion during annealing. In a process for making this, a non-dopant diffusion barrier, e.g., C, N, Si, F, etc., is implanted into the “halo” region of a semiconductor device, e.g. diode, bipolar transistor, or CMOSFET. This combined with a lower annealing budget (“Spike Annealing”) allows a steeper halo dopant profile to be generated. The invention is especially useful in CMOSFETs with gate lengths less than about 50 nm.

Diffusion barrier spikes for III-V structures

Abstract: A diffusion preventing barrier spike is disclosed. The spike prevents diffusion of dopants into another layer without forming a pn junction in the layer. The spikes are illustratively Al or an aluminum containing material such as AlAs and have a thickness on the order of 1 nm. The spikes of the present invention may be used to stop dopant diffusion out of a doped layer in a variety of III-V semiconductor structures, such a InP-based PIN devices.