Showing papers on "Parasitic capacitance published in 1996"

Accuracy of electron counting using a 7‐junction electron pump

Abstract: We have operated a 7‐junction electron pump as an electron counter with an error per pumped electron of 15 parts in 109 and an average hold time of 600 s. The accuracy and hold time are sufficient to enable a new fundamental standard of capacitance. We compare the measured accuracy of the pump as a function of pumping speed and temperature with theoretical predictions based on a model which includes stray capacitance.

Hardware design of electrical capacitance tomography systems

Abstract: Electrical capacitance tomography (ECT) was one of the techniques which were firstly developed for process tomography (PT) Two types of capacitance measuring circuits are the most suitable for the use in ECT systems - the charge/discharge circuit and the AC-based circuit - because of their immunity to stray capacitance Since the standing capacitances involved are relatively large and the capacitance changes to be measured are very small, the standing values need to be cancelled by DC offset compensation or AC feedback compensation Alternatively, the capacitances can be measured by high-accuracy self-balancing circuits without standing value compensation In this paper different designs of sensing electronics for ECT systems are presented and the advantages and disadvantages compared

Low-EMI electronic apparatus, low-EMI circuit board, and method of manufacturing the low-EMI circuit board

Abstract: A low-EMI circuit which realizes a high mounting density by converting the potential fluctuation of a power supply layer with respect to a ground layer which occurs on switching an IC device etc., into Joule's heat in the substrate without using any parts as a countermeasure against the EMI. Its structure, a circuit board using it, and a method of manufacturing the circuit board are also disclosed. Parallel plate lines in which the Q-value of the stray capacitance between solid layers viewed from the power supply layer and ground layer is equivalently reduced and which are matchedly terminated by forming a structure in which a resistor (resistor layer) and another ground layer are provided in addition to the power supply layer and the ground layer on a multilayered circuit board. A closed shield structure is also disclosed. This invention can remarkably suppress unwanted radiation by absorbing the potential fluctuation (resonance) which occurs in a power supply loop by equivalently reducing the Q-value of the stray capacitance, absorbing the standing wave by the parallel plate lines matchedly terminated and, closing and shielding the parallel plate lines.

Lumped parameter models for single- and multiple-layer inductors

Abstract: A method for modeling inductors under high-frequency operation is presented. The method is based on analytical approaches which can predict turn inductances, turn-to-turn and turn-to-core capacitances using physical structure of windings. Turn inductances, turn-to-turn and turn-to-core capacitances of coils are then introduced into suitable lumped parameter equivalent circuits of inductors. The overall inductance and stray capacitance can be obtained through the use of the equivalent circuits. Both single- and multiple-layer inductors are considered. The method was tested with experimental measurements. The accuracy of the results was good in most cases. The derived expressions can be useful for the design of HF inductors and can also be used for simulation purposes.

Clocking scheme and charge transfer switch for increasing the efficiency of a charge pump or other circuit

Abstract: An efficient charge pump circuit. Increased efficiency compared to previous pump circuits is achieved through use of a novel charge transfer switch and associated clocking scheme which reduces the supply current required to operate the charge pump. Instead of repeatedly charging and discharging a stray capacitance of each pump stage capacitor, some of the charge stored in the stray capacitor on the clock driver side is transferred to the next pump stage. This serves to pre-charge the stray capacitor of the next stage, reducing the supply current required to operate the charge pump. The apparatus and method described can also be used to reduce the power consumed by a system or circuit which has internal signals or nodes which are in opposite phase to each other. This is accomplished by reducing the power used to charge and discharge a stray capacitance associated with the signals or nodes.

Ultrafast, dual-depletion region, InGaAs/InP p-i-n detector

Abstract: The design of a new kind of photodetector, the dual-depletion region p-i-n photodetector, is presented. This vertical detector has a parasitic capacitance and transit time that can be controlled semi-independently. This eases the classical tradeoff between these two speed limiting factors, allowing the design of large, fast detectors. A theoretical analysis of the transit time effect and the capacitance effect is made. This analysis is then used to compute optimum design parameters.

Surface charges on circuit wires and resistors play three roles

Abstract: The significance of the surface electric charge densities associated with current‐carrying circuits is often not appreciated. In general, the conductors of a current‐carrying circuit must have nonuniform surface charge densities on them (1) to maintain the potential around the circuit, (2) to provide the electric field in the space outside the conductors, and (3) to assure the confined flow of current. The surface charges and associated electric field can vary greatly, depending on the location and orientation of other parts of the circuit. We illustrate these ideas with a circuit consisting of a resistor and a battery connected by wires and other conductors, in a geometry that permits solution with a Fourier–Bessel series, while giving flexibility in choice of wire and resistor sizes and location of the battery. Plots of the Poynting vector graphically demonstrate energy flow from the battery to the resistive elements. For a resistor with a large resistance, the potentials and surface charge densities around the current‐carrying circuit are nearly the same as for the open circuit with the resistor removed. For such resistors, the capacitance of a resistor and its adjacent elements, defined in terms of the surface and interface charges present while current flows, is roughly the same as the capacitance of the adjacent elements of the open circuit alone. The discussion is in terms of time‐independent currents and voltages, but applies also to low‐frequency ac circuits.

Gate capacitance attenuation in MOS devices with thin gate dielectrics

Abstract: As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate capacitance, due to the increasing importance of the carrier distributions in the silicon and polysilicon electrodes. For the first time, we quantitatively explore the combined impact of degenerate carrier statistics, quantum effects, and the semiconducting nature of the gate electrode on gate capacitance. Only by including all of these effects can we successfully model the capacitance-voltage behavior of sub-10 nm MOS capacitors. For typical devices, we find the gate capacitance to be 10% less than the oxide capacitance, but it can be attenuated by 25% or more for 4 nm oxides with polysilicon gates doped to less than 10/sup 20/ cm/sup -3/.

Suspended membrane inductors and capacitors for application in silicon MMIC's

Abstract: This paper considers the fabrication and modelling of suspended membrane inductors and capacitors on ordinary silicon substrates. A single post-processing etching step was added to an otherwise standard process. For both components, parasitic capacitances to ground are drastically reduced, enabling high frequency operation. Furthermore, the measured quality factor Q is demonstrably improved with respect to normally fabricated thin film components.

High power DPDT antenna switch MMIC for digital cellular systems

Abstract: In this paper, we propose two new types of dual-pole double-throw (DPDT) switch GaAs JFET monolithic microwave integrated circuits (MMICs) for digital cellular handsets. These ICs have the excellent characteristics of low insertion loss and high power handling capability, even with a low control voltage by stacking three JFETs with shallow V/sub p/ and using a novel bias circuit using p-n junction diodes. One DPDT switch IC has two shunt FET blocks and can achieve high isolation without external parts. An insertion loss less than 0.6 dB and isolation over 25 dB up to 2 GHz were achieved. P/sub 1dB/ was about 35 dBm even with a control voltage of 0/3 V. Another DPDT switch IC utilizes parallel resonance of external inductors and parasitic capacitance between the drain and the source of the OFF-state FETs. By attaching 15 nH inductors, for example, the IC exhibited an insertion loss as low as 0.4 dB, an isolation of better than 40 dB at 1.5 GHz, a bandwidth of about 400 MHz for 20 dB isolation, and P/sub 1dB/ of about 34 dBm with the 0/3 V control.

An interface circuit for high-accuracy signal processing of differential-capacitance transducers

Abstract: For high-accuracy signal processing of differential-capacitance transducers, an interface circuit is developed. The architecture is based on the idea that the ratio of one of the transducer capacitances to its total capacitance represents the offset binary equivalent of the physical quantity under measurement. An op amp-based capacitance-to-voltage converter is commonly used for capacitance detection and an analog-to-digital converter is used for the ratiometric operation. A circuit analysis shows that the interface can detect the capacitance change as small as 0.01% of the total capacitance. Experimental results are also given to confirm the analysis.

A gate-side air-gap structure (GAS) to reduce the parasitic capacitance in MOSFETs

Abstract: A new parasitic capacitance reduction technologies, utilizing a Gate-side Air-gap Structure (GAS), has been developed for MOSFETs. The GAS in which a 5-nm-wide air-gap was formed next to the gate reduced the fringe capacitance by half. Hence, the gate delay time was reduced by 4.8 psec at FO=1 and by 16 psec at FO=3 in a 0.25 /spl mu/m CMOS, and power consumption was lowered compared to a conventional structure. We also propose pocket implantation through the GAS to suppress short channel effects with only a slight increase in the junction capacitance.

Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits by filtering timing error bounds for layout critical nets

Abstract: A method, apparatus and computer program product performs a bounded parasitic extraction of typically all nets in an integrated circuit as part of a series of post-layout verification operations. According to one embodiment, a resistance-only extraction and/or a capacitance-only extraction is initially performed using computationally inexpensive electrical models of the nets. The resistance and capacitance extractions may be combined with models of the active devices to generate realistic worst case and best case delay models for each of the extracted nets. The delay models may be based on the resistance-only extraction and an upper bound on the parasitic capacitance of the net determined from the capacitance-only extraction, however, other models based solely on a resistance-only extraction may also be used, although they are typically less preferred. A user-specified timing error tolerance is then used to automatically determine the appropriate level of additional extraction detail to be applied to the specific nets in the integrated circuit. This gives the user direct error control over the extraction process so that the extracted netlist meets the user-specified timing error tolerance in an efficient manner.

A wireless circuit board system for a motor controller

Abstract: A multilayer circuit board system or laminated circuit board system for use in a motor controller includes a motherboard, at least one power substrate circuit board, and a capacitor circuit board. The power substrate module includes a mounting area provided in a recess, window or portion of the circuit board where the circuit board is only a single layer thick. The single circuit board layer at the mounting area provides a heat conductive yet highly electrically insulated mounting area for receiving a heat sink. The heat sink can be mounted on a side opposite the electrical device. The capacitor circuit board, power substrate circuit board, and mother circuit board are interconnected without the use of external connectors or wires. A flexible circuit board layer or SCM™ interconnect interface allows the circuit boards to be connected solely by printed circuit (PC) wires.

Stray capacitances of single-layer air-core inductors for high-frequency applications

Abstract: A method for predicting stray capacitances of HF inductors dependent on their geometry is presented. The analysis is performed for inductors made of one layer of turns with circular and rectangular cross-sections. The wire is uniformly wound around a cylindrical nonferromagnetic core. The method is based on an analytical approach to obtain the turn-to-turn and turn-to-shield capacitances of coils. The influence of insulating coatings of the wire is also taken into account. An overall equivalent stray capacitance is derived according to the typical HF equivalent lumped parameter circuit of inductors. The method was tested with experimental measurements and the accuracy of the results was good in most cases. The derived expressions are useful for designing of HF inductors and can be also used for simulation purposes.

Dc Squids: Design, Optimization and Practical Applications

Abstract: The dc Supercoducting Quantum Interference Device (SQUID) is the most sensitive sensor of magnetic flux available, with an enormous frequency response extending from dc to a few GHz. It has been shown that the energy resolution of low-inductance SQUIDs operating at 4.2 K can approach the quantum limit. Unfortunately, the small inductance required makes it difficult to couple external signals to the SQUID. Excellent coupling can be achieved using thin-film and lithographic techniques to integrate an input coil on top of a washer-shaped SQUID inductance. This approach has significantly advanced SQUID technology for numerous applications. Unless the SQUID is heavily damped, however, the parasitic elements (capacitance and inductance) that are introduced can lead to resonances in the SQUID dynamics. These resonances manifest themselves as strong irregularities in the current-voltage (I-V) and voltage-flux (V-Ф) characteristics, leading to excess noise and making operation using conventional flux modulation techniques extremely difficult. Overly damping the SQUID may reduce the excess noise, but doing so also diminishes the amplitude of the SQUID output signal, placing more stringent demands on the readout electronics.

Stray capacitances of single-layer air-core inductors for high-frequency applications

Abstract: A method for predicting stray capacitances of HF inductors dependent on their geometry is presented The analysis is performed for inductors made of one layer of turns with circular and rectangular cross-sections The wire is uniformly wound around a cylindrical nonferromagnetic core The method is based on an analytical approach to obtain the turn-to-turn and turn-to-shield capacitances of coils The influence of insulating coatings of the wire is also taken into account An overall equivalent stray capacitance is derived according to the typical HF equivalent lumped parameter circuit of inductors The method was tested with experimental measurements and the accuracy of the results was good in most cases The derived expressions are useful for designing of HF inductors and can be also used for simulation purposes

A pure CMOS surface micromachined integrated accelerometer

Abstract: A pure CMOS integrated accelerometer was realised using surface micromachining as structural technique. The samples were fabricated by a 14 mask 0.8 /spl mu/m CMOS standard process in a Siemens production line. Only the standard layers of the process (350 nm polysilicon and 600 nm oxide as sacrificial layer) are used to build up the surface micromachined device. Sensor release and antisticking are also CMOS-compatible. The movement of a seismic mass normal to the chip surface is capacitively detected (open loop) and transformed on chip into a digital output signal by a robust circuit for measuring sub-fF capacitance differences. Parasitics are suppressed on chip. The sensor was designed to measure accelerations up to 50 g. A resolution of /spl plusmn/0.6 g corresponding to a capacitance change of /spl plusmn/0.1 fF was observed.

Liquid crystal display device having uniform parasitic capacitance between pixels

Abstract: A liquid crystal display device according to the present invention includes pixels having uniform parasitic capacitance values. Each pixel comprises at least one thin film transistor. The gate electrode of the thin film transistor is formed from part of a gate line, so as to reduce the overall area occupied by the transistor. A drain electrode is formed over and within the width of the gate line and parallel to the source electrode, and having a surface area less than the underlying portion of the gate line. In addition, the source electrode and the drain electrode are isolated, but electrically connected to a semiconductor layer, from the gate electrode. A drain electrode extension is connected with the drain electrode and a pixel electrode, and projects outward over both width edges of the gate line. The drain electrode and drain electrode extension are dimensioned with sufficient margins with respect to the gate line to account for misalignments between the drain electrode and the gate line. In this way, the difference in pixel brightness due to differences in parasitic capacitance is removed by eliminating the possibility of alignment errors from varying the parasitic capacitance between pixels. Moreover, the area which the thin film transistor occupies is respectively widened compared with the prior art and the number of corrections to be made on each wiring layer is decreased because the cross steps of the gate electrode and the source electrode that occur on the underlying layer are reduced.

A self-balancing circuit to measure capacitance and loss conductance for industrial transducer applications

Abstract: This paper describes a capacitance and loss conductance measuring circuit for the use in industrial transducers. The circuit is based on self-balancing principle and it is immune to stray capacitance. The balancing process is controlled by a micro-controller. The capacitance and loss conductance are represented by the digital feedback signals or by the combination of the feedback signals with the forward path signals. Experimental results show that the circuit has high resolution (0:04 fF) and good linearity (0.999).

Method for manufacturing bipolar transistor having reduced base-collector parasitic capacitance

Abstract: In a process for manufacturing a bipolar transistor, an intrinsic base is formed by a selective epitaxial growth while the lower surface of a base electrode single crystal silicon film 33 and the surface of a collector epitaxial layer 3 are exposed. In this process, the intrinsic base 8 and an extrinsic base 34 are grown as a single crystal to form a self-alignment type bipolar transistor having a reduced parasitic capacitance between the base and the collector.

A 2.1 MHz Crystal Oscillator Time Base with a Current Consumption under 500 nA

Abstract: A micro-power circuit is encapsulated with a 2.1 MHz ZT-cut quartz in a vacuum package. The oscillator core has 2 complementary active MOSFETS and amplitude stabilization. New coupling and biasing circuits, and dynamic frequency dividers allow to achieve ±2 ppm frequency stability down to 1.8 V with a current under 0.5 ?A.

High Q-factor inductors integrated on MCM Si substrates

Abstract: High quality factor (Q) inductors were designed and fabricated on high-resistivity (2000 /spl Omega//spl middot/cm) Si substrates with multichip module (MCM) fabrication technology. A Q-factor of 30 was achieved for an inductor of 4 nH at 1-2 GHz. To enhance the Q-factor and reduce the parasitic coupling capacitance, a staggered double metal-layered structure was utilized by taking advantage of the double-layered metal lines in MCM. With electromagnetic simulation tools, computer-aided analysis was used to optimize the device characteristics. The skin effect and the lossy substrate effect on the performance of the radio frequency (RF) thin-film inductors were studied. The fabrication process used polyimide as the dielectric layer and aluminum as the metal layer. The use of the low dielectric-constant material, polyimide, reduces the parasitic coupling capacitance between metal lines and increases the quality factor and the self-resonant frequency for the RF integrated inductors.

Semiconductor integrated circuit device having minature multi-level wiring structure low in parasitic capacitance

Abstract: After a pattern transfer of a first pattern image to a lower photo-sensitive layer of first material, a second pattern image is transferred to an upper photo-sensitive layer of second material higher in photo-sensitivity than the first material, and the first image and the second image are concurrently developed so as to form a composite etching mask through a simple process.

Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers

Abstract: Measurements of a 0.5 /spl mu/m CMOS testchip using several techniques have demonstrated a reduction in the generation of ground bounce. These techniques are: an automatic transistor sizing method that compensates for process, temperature, and supply voltage variations; a self-adjusting internal capacitive load that counteracts the increased switching rate of faster parts; and an integrated resistive element inserted directly into the power and ground leads that dampens the RLC oscillations. Comparison measurements between a conventional buffer and the new buffer have demonstrated that the amplitude and duration of the generated ground bounce has been reduced 2.5/spl times/ and 2/spl times/, respectively. A single external resistor is required to set a reference current.

A very accurate measurement system for multielectrode capacitive sensors

Abstract: A very accurate capacitance-measurement system consisting of a discrete capacitance-dependent oscillator and a microcontroller has been developed. It can measure multielectrode capacitors with capacitances up to 2 pF, with an accuracy of 100 ppm with respect to a reference capacitor. The resolution amounts to 50 aF with a total measurement time of 300 ms.

Device characteristics of a 30-V-class thin-film SOI power MOSFET

Abstract: A 30-V thin-film SOI power MOSFET having a tungsten polycide gate with a linear gate topology has been fabricated at a practical device level. Its electrical characteristics were successfully demonstrated for the first time. The experimental device has 1010 unit cells and a total gate width of 4.04 cm, It has a specific on-resistance of 92 m/spl Omega//spl middot/mm/sup 2/ and breakdown voltage of 33 V. The device's various parasitic capacitance characteristics were measured and compared with those of a lateral power MOSFET fabricated on a bulk-silicon substrate.

Sampling circuit charge management

Abstract: The detrimental nonlinear charging currents from an analog input signal through an anti-aliasing filter into a sampling circuit can be minimized by using primary and secondary inputs to the sampling circuit. The secondary input is turned on before the primary input and the charge required to charge the parasitic capacitance inside the sampling circuit and to replenish the channeling charge lost in the previous cycle is supplied primarily through the secondary input. Immediately after the secondary input is turned off the primary input is connected to the sampling node, and only the charge required to fine tune the signal into the sampling capacitor is drawn through the primary input. Therefore, most of the non-linear charge injection is passed through the secondary input, and the signal passed through the primary input is used to fine tune the voltage levels inside the sampling circuit during the actual sampling operation.

Electronic devices comprising thin-film circuitry

Abstract: A large-area electronic device such as, e.g., a large-area image sensor or flat panel display comprises thin-film drive circuitry including inverters each comprising a driver TFT (M1), a load TFT (M2) and a bootstrap capacitor (Cs). Most TFT types which may be used to fabricate the transistors (M1 and M2) have a high parasitic gate capacitance due, inter alia, to overlap of the gate electrode (g) with their source and drain electrode (21 and 22). This parasitic capacitance degrades the inverter gain Av by coupling between the output line (O/P) of the inverter and the gate electrode (g) of its load device (M2) and an excessively large capacitor (Cs) is required to overcome this degradation. The present invention uses a reduction in the transconductance (gm2) of the load TFT (M2) to permit a reduction in the size of the boot strapping capacitor (Cs) to within practical limits, while still obtaining a desirably high gain Av from the inverter in spite of the parasitic capacitances. A factor ν.C in gm 2 of the load TFT (M2) is reduced for this purpose, for example by having a gate dielectric (24) of greater thickness (t2) or lower dielectric constant, and/or a lower crystallinity or amorphous material (α-Si) for the channel region (206). These same different materials or thicknesses as used for the driver and load TFTs (M1 and M2) may also be used to advantage in the bootstrap capacitor (Cs) and in a switch (M3) for the capacitor (Cs).

Anti-punchthrough ion implantation for sub-half micron channel length MOSFET devices

Abstract: A method for forming a MOSFET device, with reduced exposure to source and drain leakage currents, that can arise due to a junction depletion punchthrough phenomena, has been developed. An anti-punchthrough, ion implantation, is performed in a confined area below the channel region. The ability to confine the area used for the anti-punchthrough region, results in protection against leakage, however with only a minimum of parasitic capacitance increase. The confined, anti-punchthrough region is obtained via ion implantation procedures into a channel region, using polysilicon sidewalls for purposes of placing the implanted region only into desired regions below the channel region.