Showing papers on "Power integrity published in 2010"

Overview of Power Integrity Solutions on Package and PCB: Decoupling and EBG Isolation

Abstract: Mitigating power distribution network (PDN) noise is one of the main efforts for power integrity (PI) design in high-speed or mixed-signal circuits. Possible solutions, which are based on decoupling or isolation concept, for suppressing PDN noise on package or printed circuit board (PCB) levels are reviewed in this paper. Keeping the PDN impedance very low in a wide frequency range, except at dc, by employing a shunt capacitors, which can be in-chip, package, or PCB levels, is the first priority way for PI design. The decoupling techniques including the planes structure, surface-mounted technology decoupling capacitors, and embedded capacitors will be discussed. The isolation approach that keeps part of the PDN at high impedance is another way to reduce the PDN noise propagation. Besides the typical isolation approaches such as the etched slots and filter, the new isolation concept using electromagnetic bandgap structures will also be discussed.

Progress Review of Electromagnetic Compatibility Analysis Technologies for Packages, Printed Circuit Boards, and Novel Interconnects

Abstract: The ever-increasing demands of digital computing and wireless communication have been driving the semiconductor technology to change with each passing day. Modern electronic systems integrate more complex components and devices, which results in a very complex electromagnetic (EM) field environment. EM compatibility has become one of the major issues in ICs redesign, mainly due to the lack of efficient and accurate simulation tools and expertise on noise reduction and immunity improvement. This paper reviews the state of the arts of IC, electronic package, and printed circuit board simulation and modeling technologies. It summarizes the modeling technologies for both available structures [multilayered power-ground planes and macromodeling of interconnect (INC)] and novel structures (nano-INCs and 3-D ICs based on through-silicon via technology). It also illustrates the trends of simulation and modeling technologies in EM compatibility, signal integrity, and power integrity.

Designing and Modeling for Power Integrity

Abstract: After providing an overview of the state-of-the-art in power distribution design and modeling, this paper focuses on return path discontinuities (RPDs) for I/O signaling. After briefly describing their importance in the context of simultaneous switching noise, a specific case of RPD based on via discontinuities is discussed in detail in the context of both the frequency- and time-domain waveforms using a test vehicle. The modeling of RPD in practical packages and printed circuit boards is addressed along with substrate coupling due to nonideal reference planes. Finally, a high-impedance power distribution scheme for I/O signaling is presented that can potentially solve a number of RPD-related problems, followed by future challenges.

Dependability in Electronic Systems: Mitigation of Hardware Failures, Soft Errors, and Electro-Magnetic Disturbances

Abstract: Introduction.- Terrestrial Neutron-Induced Failures in Semiconductor Devices and Relevant Systems.- Electromagnetic Compatibility Power Integrity.- Dependable System Technology.

Signal/Power Integrity Analysis for Multilayer Printed Circuit Boards Using Cascaded S-Parameters

Abstract: A cascaded S-parameter method is proposed in this paper for signal/power integrity analysis of multiple vias in a multilayer printed circuit board (PCB). The proposed method enables efficient and accurate construction and simulation of physics-based via model for complex multilayer PCB structures involving vias. The physics-based via model describes the parasitic effects near each via region as well as mutual coupling among different vias. In this model, each via portion between two parallel plates is regarded as a three-port network with two coaxial ports and one radial port between the two plates. A procedure is first developed to obtain the S-parameters of a single plate pair, which combine the three-port via networks with the impedance matrix of the parallel-plate pair. Once the S-parameters of each plate pair are obtained, an assembling technique for cascading microwave networks is further developed. The method proposed in this paper has been validated by both simulations with a commercial circuit simulator and measurements.

Impact of Shorting Vias Placement on Embedded Planar Electromagnetic BandGap Structures Within Multilayer Printed Circuit Boards

Abstract: This paper investigates the power integrity behavior of planar electromagnetic bandgap (EBG) structures embedded between two solid layers within the stack-up of a multilayer printed circuit board. The bandgap generation and power integrity performance of the embedded EBG can be achieved only by placing vias shorting the solid planes above and below the patterned layer. The vias inhibit the resonances of the cavity made by the two solid planes, ensuring the designed bandgap, as if the planar EBG was laid out on an outer stack-up layer. The impact of the stitching vias' number and location is addressed and the concepts of regular, global, random, or local via placement are introduced.

IR-DROP Analysis and Thermal Assessment of Planar Electromagnetic Bandgap Structures for Power Integrity Applications

Abstract: This paper investigates the relationship among the high-frequency performances of a planar electromagnetic bandgap structure for power integrity applications and its static (dc) behavior. The IR-Drop and the thermal performances are accurately investigated through 3-D simulations. Measurements of the high-frequency electromagnetic properties and of the temperature variation are also performed for validating the models employed in the analysis.

Design of a Common Mode Filter by Using Planar Electromagnetic Bandgap Structures

Abstract: In this paper, an embedded electromagnetic bandgap structure is proposed for harmonic filtering of differential signal's undesired common mode components. Rather than use lumped circuit components and likely causing some degradation to the intended high speed differential signal, the embedded planar common mode filter causes no degradation to the intended signal, and enhances the signal integrity and electromagnetic compatibility performance of the system. Single ended and differential traces are considered and the impact of the common mode filtering is measured in terms of mixed mode scattering parameters and eye diagram metrics. The systematic procedure to design such a structure is outlined, and its design robustness is also verified.

Systematic Microwave Network Analysis for Multilayer Printed Circuit Boards With Vias and Decoupling Capacitors

Abstract: An efficient microwave network method is proposed for signal and power integrity analysis of a multilayer printed circuit board with multiple vias and decoupling capacitors. The multilayer parallel plate structure is described as a cascaded microwave network. The admittance matrix of a single plate pair with ports defined in via holes both on top and bottom plates is obtained through the intrinsic via circuit model and impedance matrix between two plates. A recursive algorithm is provided to obtain the combined admittance matrix of two layers of plate pair coupled through via holes on a common plate. Decoupling capacitors are naturally treated as impedance loads to the cascaded admittance network. Numerical simulations and measurements have been used to validate the method and good agreements have been observed. While the method is as accurate as full-wave numerical solvers, it achieves much higher efficiencies both in CPU time and memory requirements.

Special Issue on PCB Level Signal Integrity, Power Integrity, and EMC

Abstract: The 24 papers in this special issue highlight recent significant advancements and innovations related to printed circuit board (PCB) signal integrity (SI), power integrity (PI), electromagnetic emission and susceptibility modeling, design, and measurement technologies.

Signal/Power Integrity Modeling of High-Speed Memory Modules Using Chip-Package-Board Coanalysis

Abstract: Under the platform of a high-speed double-data-rate three (DDR3) memory module, a modeling method considering all the significant effects from the chip, package, and board levels is developed to identify and investigate the critical nets affecting the signal or power integrity (SI/PI). For SI part, accurate modeling strategies for signal channels are verified by experiments on samples of address lines. The following what-if analyses of eye diagrams help to identify the discontinuities of package trace to be the bottlenecks and have great effects on the eye diagrams. For PI issues, the modeling methodologies for power distribution networks of data buses are demonstrated and validated with the results of measurement. The analysis indicates that the parasitic effects of the low-cost package structure are the most critical, depicting the importance of improved package design in the next-generation DDR memory modules.

Partial EBG Structure with DeCap for Ultra-wideband Suppression of Simultaneous Switching Noise in a High-Speed System

Abstract: To supply a power distribution network with stable power in a high-speed mixed mode system, simultaneous switching noise caused at the multilayer PCB and package structures needs to be sufficiently suppressed. The uni-planar compact electromagnetic bandgap (UC-EBG) structure is well known as a promising solution to suppress the power noise and isolate noise-sensitive analog/RF circuits from a noisy digital circuit. However, a typical UC-EBG structure has several severe problems, such as a limitation in the stop band’s lower cutoff frequency and signal quality degradation. To make up for the defects of a conventional EBG structure, a partially located EBG structure with decoupling capacitors is proposed in this paper as a means of both suppressing the power noise propagation and minimizing the effects of the perforated reference plane on the signal quality. The proposed structure is validated and investigated through simulation and measurement in both frequency and time domains. Keywords: Electromagnetic bandgap (EBG), signal integrity (SI), power integrity (PI), simultaneous switching noise (SSN), decoupling capacitor (DeCap).

Integral-Equation Equivalent-Circuit Method for Modeling of Noise Coupling in Multilayered Power Distribution Networks

Abstract: Power distribution networks are the major source of noise coupling in high-speed and high-density electronic packages and printed circuit boards. We present the integral equation hybrid with the modal decoupling as a simple and efficient method for the modeling of multilayered power distribution networks. In this method, the power distribution network is decoupled into three simple parts: power-ground planes, signal traces, and multihole vias. For the through-hole vias, we propose a nonequipotential transmission lines model to represent their parasitic circuits. An accurate and efficient de-embedding method is used to extract the parameters inside the models. It accounts for losses and irregular shapes of substrates and conductors. Finally, the equivalent circuits of each part of power distribution network are integrated to perform the system-level signal and power integrity analysis. The accuracy and efficiency of the proposed method are validated through comparison with the measurement and full-wave analysis.

Design and Implementation of a Novel Hybrid Photonic Crystal Power/Ground Layer for Broadband Power Noise Suppression

Abstract: By embedding periodically high-K rods in the package substrate, a hybrid photonic crystal power/ground layers (PCPL) is proposed with stopband enhancement for power/ground noise suppression. The hybrid PCPL consists of two different lattice structures, which have the same pitch but different radii of the high-K rods. Using the gap map of the photonic crystal lattice, the enhanced stopband can be synthesized by designing these two different lattices with compensated stopband. An implementation approach, which is compatible to the standard fabrication process of package or printed circuit board (PCB), is also proposed in this paper. The high-K rods are considered as surface mount technology (SMT)-like components and ring-shaped soldering pads with through-hole-via connecting to power/ground planes are designed on the package substrate. A test sample of the hybrid PCPL is fabricated and measured. A wide stopband from 3.2 to 9.5 GHz is achieved with 30 dB of noise suppression in average. This enhanced stopband is consistent with the prediction both by gap map synthesis and full-wave simulation. The hybrid PCPL is applied in a package substrate with voltage-controlled oscillator (VCO) circuit and excellent noise suppression performance is demonstrated.

On Vector Fitting methods in signal/power integrity applications

Abstract: Vector Fitting (VF) has been applied to reformu- late traditional system identification techniques by introducing a partial-fraction basis to avoid ill-conditioned calculation in broadband system identifications. Because of the reliable and versatility of VF, many extensions and applications have been proposed, for example, the macromodeling of linear structures in signal/power integrity analyses. In this paper, we discuss the macromodeling framework and some main features in VF in terms of data, algorithms and models. Finally, an alternative P -norm approximation criterion is proposed to enhance the macromodeling process.

System and method for adapting electrical integrity analysis to parametrically integrated environment

Abstract: A system and method is provided for generating a programmably implemented model which emulates a power delivery network serving an integrated circuit (IC) core in an electronic system. The system and method generally comprise measures for establishing a power integrity (PI) topology including models for a voltage regulator module that generates at least one predetermined supply voltage level, and for a conductive power rail portion of the power delivery network (PDN). The system and method further comprise measures for interconnecting to the conductive power rail portion model a first behavioral model indicative of the current consumption characteristics of the IC core, and a second behavioral model indicative of the current consumption of an IO interface buffer driving an output signal of the electronic system.

System and method for implementing power integrity topology adapted for parametrically integrated environment

Abstract: A system and method are provided for generating a programmably implemented model which emulates a power delivery network serving an integrated circuit (IC) core in an electronic system. The system and method generally comprise measures for establishing a power integrity (PI) topology including models for a voltage regulator module that generates at least one predetermined supply voltage level, and for a conductive power rail portion of the power delivery network (PDN). The system and method further comprise measures for interconnecting to the conductive power rail portion model a first behavioral model indicative of the current consumption characteristics of the IC core, and a second behavioral model indicative of the current consumption of an IO interface buffer driving an output signal of the electronic system.

Fast Physics-Based Via and Trace Models for Signal and Power Integrity Co-Analysis

Abstract: Physics-based models for vias and traces including new component models are applied to simulate multilayer interconnects on printed circuit boards. A variety of interconnect structures, including via arrays and differential links between package via fields, are studied with model-to-hardware correlation. These models also enable efficient signal integrity and power integrity co-analysis with focus on modeling simultaneous switching noise coupled into high-speed signal nets as well as understanding the effects of decoupling capacitor placement. Simulation time has been reduced at least three orders of magnitude with respect to comparable full-wave simulations. Author’s Biographies Xiaoxiong Gu received the B.S. degree from Tsinghua University, Beijing, China, in 2000, the M.S. degree from the University of Missouri, Rolla, in 2002, and the Ph.D. degree from the University of Washington, Seattle, in 2006, all in electrical engineering. He is currently a Research Staff Member with the IBM T. J. Watson Research Center. His research interests include characterization of high-speed interconnect and microelectronic packaging, signal integrity and computational electromagnetics. Dr. Gu received the best paper award at ECTC in 2007 and DesignCon Paper Award in 2008. Renato Rimolo-Donadio received the B.S. and Lic. degrees in electrical engineering from the Technical University of Costa Rica (ITCR), Costa Rica, in 1999 and 2004, respectively, and the M.S. degree in microelectronics and microsystems from the Technical University of Hamburg-Harburg (TUHH), Germany, in 2006, where he is currently working toward the Ph.D. degree in electrical engineering. Since November 2006, he has been a Scientific Research Assistant at the Institute of Electromagnetic Theory, Technical University of Hamburg-Harburg. His main research interests include system level modeling and optimization of interconnects, and analysis of signal and power integrity problems at PCB and package level. Francesco de Paulis received his Laurea degree and his Specialistic degree (summa cum laude) in Electronic Engineering from University of L’Aquila, L’Aquila, Italy, in 2003 and 2006, respectively. He was involved in the research activities of the UAq EMC Laboratory from August 2004 to August 2006. From June 2004 to June 2005 he had an internship at Selex Communications s.p.a. within the layout/SI/PI design group. In August 2006 he joined the EMC Laboratory at the Missouri University of Science and Technology (formerly University of Missouri-Rolla), where he pursued a Master of Science Degree in Electrical Engineering in May 2008. He is currently enrolled in PhD program at the University of L’Aquila, L’Aquila, Italy. His main research interests are in developing fast and efficient analysis tool for SI/PI design of high speed signal on PCB, RF interference in mixed-signal system, EMI problem investigation on PCBs. Zhenwei Yu received his B.S. degree in Mathematics and Physics, and M.S. degree in Electrical Engineering from Tsinghua University, Beijing, China, in 2005 and 2007 respectively. Currently he is a Ph.D. candidate with the EMC Laboratory at Missouri University of Science and Technology (formerly University of Missouri-Rolla). His research interests include modeling of IC emissions, RF interference, PCB noise mitigation, and tool development for Signal Integrity and Electromagnetic Compatibility designs in high-speed PCBs. He was a Co-op at IBM, Research Triangle Park, NC, from January to July 2009 and worked in the EMC modeling tool development. Young H. Kwark received his BSEE from the Massachusetts Institute of Technology and his MSEE/PhD from Stanford University. His work experience as a Research Staff Member at the IBM T. J. Watson Research Center, Yorktown Heights, NY, includes circuit design for optical links and wireless applications. He is currently involved in package characterization for high performance computing platforms. Dr. Kwark received DesignCon Paper Awards in 2005, 2006 and 2008. Matteo Cocchini received his Laurea (5-year degree) in Electronic Engineering in June 2006 from University of L'Aquila, L'Aquila, Italy, where he got involved in the research activities of the UAq EMC Laboratory in 2005 and 2006. In August 2006, he joined the MST EMC Lab at the Missouri University of Science and Technology, where his research activity included via transition modeling and power distribution network simulations. He got a Master of Science in Electrical Engineering from the same University in May 2008. He currently works as Signal and Power Integrity Engineer for the IBM I/O packaging and development team in Poughkeepsie, New York. Mark B. Ritter received a B.S. degree in physics from Montana State University in 1981 and M.S., M.Phil. and Ph.D. degrees in Applied Physics from Yale University in 1987. His work at IBM has focused on high-speed I/O circuit and package design, with work including Fibre Channel, 10 Gb/s Ethernet, and 40 Gb/s analog front end circuits as well as interconnect structures for high-speed data transmission. Dr. Ritter presently manages a group focusing on high-speed I/O subsystems. Dr. Ritter was the recipient of the 1982 American Physical Society Apker Award and DesignCon Paper Award in 2008. Bruce Archambeault is a Senior Technical Staff Member at IBM in Research Triangle Park, NC. He received his B.S.E.E degree from the University of New Hampshire in 1977 and his M.S.E.E degree from Northeastern University in 1981. He received his Ph. D. from the University of New Hampshire in 1997. Dr. Archambeault has authored or co-authored a number of papers in computational electromagnetics, mostly applied to real-world EMC applications. He is currently a member of the Board of Directors for the IEEE EMC Society and a past Board of Directors member for the Applied Computational Electromagnetics Society (ACES). He has served as a past IEEE/EMCS Distinguished Lecturer and Associate Editor for the IEEE Transactions on Electromagnetic Compatibility. Albert E. Ruehli received his Ph.D. degree in Electrical Engineering in 1972 from the University of Vermont, and an honorary Doctorate in 2007 from the Lulea University in Sweden. He has been a member of various projects with IBM including interconnect tools and modeling and manager of both a VLSI design and CAD group. From 1972 to 2009, he was with IBM’s T.J. Watson Research Center. Currently, he is an Adjunct Professor at the Missouri University of S&T and an Emeritus at IBM. He is the editor of two books and author or coauthor of over 180 technical papers. He received five IBM Awards, the Guillemin-Cauer Prize in 1982, and the Golden Jubilee Medal from the IEEE CAS Society in 1999. He received a Certificate of Achievement from the IEEE EMC society in 2001, the 2005 Richard R Stoddart Award, and in 2007 he received the Honor ary Life Member Award from the IEEE EMC Society and is a Life Fellow of the IEEE and a member of SIAM. Jun Fan received his B.S. and M.S. degrees in Electrical Engineering from Tsinghua University, Beijing, China, in 1994 and 1997, respectively. He received his Ph.D. degree in Electrical Engineering from the University of Missouri-Rolla in 2000. From 2000 to 2007, he worked for NCR Corporation, San Diego, CA, as a Consultant Engineer. In July 2007, he joined the Missouri University of Science and Technology (formerly University of Missouri-Rolla), and is currently an Assistant Professor with the UMR/MS&T EMC Laboratory. His research interests include signal integrity and EMI designs in high-speed digital systems, dc power-bus modeling, intra-system EMI and RF interference, PCB noise reduction, differential signaling, and cable/connector designs. Dr. Fan serves as the Chair of the TC-9 Computational Electromagnetics Committee, the Secretary of the Technical Advisory Committee, and a Distinguished Lecturer of the IEEE EMC Society. Christian Schuster received the Diploma degree in physics from the University of Konstanz, Germany, in 1996, and the Ph. D. degree in electrical engineering from the Swiss Federal Institute of Technology (ETH), Zurich, Switzerland, in 2000. From 2001 to 2006 he was a Research Staff Member at the IBM T. J. Watson Research Center, Yorktown Heights, NY. Since October 2006, Dr. Schuster is a full professor of electrical engineering at the Technische Universität Hamburg-Harburg (TUHH), Germany. Dr. Schuster received DesignCon Paper Awards in 2005 and 2006. He is a senior member of the IEEE.

Signal and Power Integrity Analysis of Differential Lines in Multilayer Printed Circuit Boards With Embedded Electromagnetic Bandgap Structures

Abstract: In this paper, the analysis of the signal integrity and the power integrity (PI) performance of different types of electromagnetic bandgap structures (EBGs) in presence of differential (DIFF) striplines is proposed. Four different configurations of 2-D embedded EBG layers are analyzed. A test vehicle consisting in a 12-layer printed circuit board in standard FR4 material is built, and the measured results (validated by means of 3-D electromagnetic simulations) are used to estimate the signal quality in terms of the transmission parameter S21, time-domain reflectometry, and eye pattern at the terminations. The PI is, instead, analyzed by means of the noise coefficient from the source to different positions along the planes (S21). Results confirm the reliability of 2-D EBGs for noise mitigation and the enhancement in the signal quality when DIFF signals are used.

Signal Integrity Enhanced EBG Structure With a Ground Reinforced Trace

Abstract: In general, a conventional electromagnetic bandgap (EBG) structure efficiently suppresses simultaneous switching noise (SSN) over a wide frequency range. However, it is difficult to apply the geometry to the design of a real printed circuit boards (PCBs) for high-speed digital circuits due to the degradation in the signal integrity performance. In this paper, a ground reinforced trace (GRT) is added to the EBG power plane to guarantee power integrity (PI) as well as signal integrity (SI) simultaneously. In addition, the definition of a noise suppression bandwidth in an EBG structure is derived for the purpose of analyzing the correlation between the GRT and the noise suppression bandwidth. This correlation is utilized to decide the location of the GRT to mitigate the degradation of the low-pass cutoff frequency. As a result, an excellent signal performance is achieved without any degradation of the noise suppression bandwidth in a conventional EBG structure.

Power Integrity Analysis for High-Speed PCB

Abstract: In high-speed digital circuit, supplying a clear power to the integrated circuit and managing the coupling of power noise which can cause fluctuations or disturbances in the power distribution system have become the bottleneck of high-speed digital circuit designs. So it is expected to be a challenging problem for the power integrity (PI) design due to the wider bandwidth of the noise. Keeping the power distribution network (PDN) impedance very low in a wide frequency range and reduce simultaneous switching noise (SSN) are priority ways for the power integrity (PI) design. The decoupling capacitors are conventionally used to minimize the power impedance at a frequency where the impedance of the decoupling capacitor is lower than that of the power/ground planes pair. This paper investigates both in time and frequency domains the power integrity with the help of full-wave finite-element simulations. The solution which is based on the decoupling capacitors is reviewed in this paper. Besides, the placement and value of the decoupling capacitors will be discussed.

Power integrity analyzer, power integrity analysis method, and program

Abstract: A power integrity analyzer according to an exemplary aspect of the invention includes a parameter inputting unit that inputs parameters to a power-supply current waveform which indicates a variation of a power-supply current value on a time axis of an element, a conversion unit that converts the power-supply current waveform which indicates a variation on the time axis determined by the parameter to a power-supply current spectrum which indicates a variation of the power-supply current value on a frequency axis, an allowable value information storage unit that stores an allowable power-supply voltage fluctuation value of the element, and an impedance calculating unit that calculates a target impedance spectrum on the device indicating the variation of impedance value on the frequency axis based on the power-supply current spectrum and the allowable power-supply voltage fluctuation value.

Modeling and design for beyond-the-die power integrity

Abstract: Power integrity gains growing importance for integrated circuits in 45nm technology and beyond. This paper provides a tutorial of modeling and design for beyond the die power integrity. We explain the background of simultaneous switching noise (SSN) and its impacts on circuit designs. We discuss various models of different accuracy and complexity for the board, package and chip, and suggest how to select proper ones for board-package-chip co-simulation and co-design of SSN. We then review different design techniques to suppress SSN, including I/O planning and placement, decoupling capacitor allocation, package layer stacking and power/ground plane stapling.

Power delivery network design and optimization for 3D stacked die designs

Abstract: Power delivery network (PDN) design is already a challenging problem for single die designs using advanced process technologies. For systems created using stacked dies with TSVs, several additional issues that affect power delivery and reliability have to be addressed. In stacked die configuration, the dies higher up in the stack-up experience additional drop and noise in their power supply as it propagates through the TSV networks of one or more dies placed lower in the stack-up. For the lower dies, the presence of the TSV farm and associated metals/vias affects the homogeneity of their own power delivery network. And if multiple dies share power and ground domains, then there could be an inter-die propagation of supply noise. So it becomes important that a PDN design and optimization flow for stacked die designs models and analyzes the presence of multiple dies and also the switching and the noise impact from the dies on each other. The analysis could be concurrent or model based, depending upon whether full databases for all the chips are available or their electrically equivalent models such as Chip Power Model (CPM) are available, respectively. For both of these approaches, a DC and time-domain analysis has to be done at the chip layout level to accurately predict the power/ground noise in the stacked die design. These analyses need to done starting early, in order to enable prototyping and design trade-off decisions. In this paper, a prototyping and verification solution for multi-die TSV based designs is outlined along with results from various design decisions undertaken.

Simulation for power integrity to design a PCB for an optimum cost

Abstract: One of the biggest design challenges today is to properly design, manufacture, simulate and validate a Power Distribution Network (PDN) in systems with increasing speed, power dissipation and density. PDN are typically comprised of capacitors networks that have several types of capacitors and values to obtain target impedance over the required frequency range for the power/ground planes on PCBs. Capacitors provide a temporary source of localized energy for instantaneous current demands from an IC, and a low-impedance return path for high frequency noise. This paper propose a simulation test for a 4 layer PCB, with power/ground planes, to evaluate the effectiveness and importance of decoupling capacitors, using tools and methodologies to determine the important factors like performance, cost and board area.

Power Integrity Analysis and Management for Integrated Circuits

Abstract: The focus of the book is squarely on integrated circuits and power integrity as it pertains to such components. It is intended both for the student engineer gaining an introduction to the field of integrated circuit design, and for those skilled in the art, developing systems based on integrated components. Hence, every attempt has been made to emphasize basic concepts, principles, and intuitive understanding, while also discussing state-of-the-art and advanced concepts and technologies. This book differs from prior, related efforts at least in that it emphasizes comprehensive, true-physical modeling of integrated circuits and systems behavior. Beginning with an intuitive understanding of power integrity in a fundamental, physical sense, through analogies with mechanical systems and their underlying laws, we explore root causes for a rise to predominance of power integrity as a performance differentiator for integrated circuits.

A Decade of Vector Fitting Development: Applications on Signal/Power Integrity

Abstract: Vector Fitting (VF) has been introduced as a partial‐fraction basis response fitting methodology for over a decade. Because of its reliability and versatility, VF has been applied and extended to a number of areas. In this book chapter, we will discuss the applications of VF in the context of macromodeling of linear structures in signal/power integrity analyses. We will also discuss main features of VF along three directions: data, algorithms and models. Two practical examples are given to demonstrate the merits of VF. An alternative P‐norm approximation criterion is proposed to enhance the accuracy of the macromodeling process.

A Domain Decomposition Approach for Efficient Electromagnetic Analysis of the Power Distribution Network of Packaged Electronic Systems

Abstract: A versatile electromagnetic modeling methodology is presented that is most suitable for use in the computer-aided design of the power distribution network (PDN) of packaged electronics. The method is characterized by modeling flexibility and computational efficiency. These attributes stem from the adoption of a modular approach for the development of the model, where the fine-feature, geometric discontinuities in the network, such as pins, vias, and splits in metallization layers, are modeled separately from the solid planar ground and power metallization portions. In this manner, multiport network models of these discontinuities are developed, making possible their expedient insertion in a discrete electromagnetic model for the solid portions of the metallization. The latter is based on a 2-D integral equation model for the cylindrical transverse electromagnetic field behavior between the metallization planes, for which only electrically important features are preserved and modeled. The utilization of a systematic decomposition approach further enhances the modeling versatility of the proposed method and enables the development of a modeling methodology that is suitable for computer-aided iteration in the electromagnetic performance-aware design of multilayer PDNs. Validation studies are used to demonstrate the efficiency of the proposed methodology and assess its accuracy as a computer-aided tool for PDN predesign.

Wideband ssn suppression in high-speed pcb using novel planar ebg

Abstract: Simultaneous switching noise (SSN) is a signiflcant problem in high-speed circuits. To minimize its efiect and improve the electrical characteristics of circuits such as signal integrity (SI) and power integrity (PI), a novel power plane with planar electromagnetic bandgap (EBG) structure is proposed for SSN suppression in printed circuit boards (PCB) in this paper. In which a kind of improved long bridge is used and the equivalent parallel inductance can be increased signiflcantly. Compared to the typical spiral bridge EBG structure with the same parameters, the long bridge EBG structure will change bandgap into dual-band, with lower center frequency and wider bandwith. The efiectiveness and accuracy of this structure are verifled by both simulations and measurements.