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Showing papers on "Relaxation oscillator published in 2012"


Journal ArticleDOI
TL;DR: An energy-efficient capacitive-sensor interface with a period-modulated output signal that converts the sensor capacitance to a time interval, which can be easily digitized by a simple digital counter, based on a relaxation oscillator consisting of an integrator and a comparator.
Abstract: This paper presents an energy-efficient capacitive-sensor interface with a period-modulated output signal. This interface converts the sensor capacitance to a time interval, which can be easily digitized by a simple digital counter. It is based on a relaxation oscillator consisting of an integrator and a comparator. To enable the use of a current-efficient telescopic OTA in the integrator, negative feedback loops are applied to limit the integrator's output swing. To obtain an accurate ratiometric output signal, auto-calibration is applied. This eliminates errors due to comparator delay, thus enabling the use of a low-power comparator. Based on an analysis of the stability of the negative feedback loops, it is shown how the current consumption of the interface can be traded for its ability to handle parasitic capacitors. A prototype fabricated in 0.35 μm standard CMOS technology can handle parasitic capacitors up to five times larger than the sensor capacitance. Experimental results show that it achieves 15-bit resolution and 12-bit linearity within a measurement time of 7.6 ms for sensor capacitances up to 6.8 pF, while consuming only 64 μA from a 3.3 V power supply. Compared to prior work with similar performance, this represents a significant improvement in energy efficiency.

128 citations


Proceedings ArticleDOI
13 Jun 2012
TL;DR: A sub-μW, 1-cycle start-up CMOS relaxation oscillator has been developed with a feedforward period control scheme and a digitally-controlled boost charging technique and it has demonstrated 100kHz clock generation with ±1%-accuracy and an extremely low power consumption of 280nW.
Abstract: A sub-μW, 1-cycle start-up CMOS relaxation oscillator has been developed with a feedforward period control scheme and a digitally-controlled boost charging technique. The oscillator is implemented in 90nm CMOS and we sucessfuly have demonstrated 100kHz clock generation with ±1%-accuracy and an extremely low power consumption of 280nW.

116 citations


Proceedings ArticleDOI
Keng-Jan Hsiao1
13 Jun 2012
TL;DR: A self-chopped relaxation oscillator with adaptive supply generation provides the stable output clock against variations in temperature and supply voltages and is implemented in a 60-nm CMOS technology.
Abstract: A self-chopped relaxation oscillator with adaptive supply generation provides the stable output clock against variations in temperature and supply voltages. The frequency drift is less than ±0.1% for the supply voltage changing from 1.6 to 3.2 V and ±0.1% for a temperature range from −20 to 100°C, which is reduced by 83% with the self-chopped technique. This relaxation oscillator is implemented in a 60-nm CMOS technology with its active area equals to 0.048 mm2. It consumes 2.8 uA from a 1.6-V supply.

71 citations


Journal ArticleDOI
TL;DR: This paper introduces a new simple Schmitt trigger circuit using a plus-type differential voltage-current conveyor (DVCC+) and only two grounded resistors and enjoys adjustable lower and higher threshold voltages as well as the output saturation levels.
Abstract: This paper introduces a new simple Schmitt trigger circuit using a plus-type differential voltage-current conveyor (DVCC+) and only two grounded resistors. The proposed circuit is very simple and enjoys adjustable lower and higher threshold voltages as well as the output saturation levels. The application of the proposed Schmitt trigger circuit to the square/triangular wave generator is also given. Moreover, a current feedback operational amplifier (CFOA)-based square/triangular wave generator is derived from the proposed DVCC+-based circuit. Simulation and experimental results are presented to exhibit the performance of the proposed circuits.

66 citations


Journal ArticleDOI
TL;DR: A quantitative analysis of the effect in Van der Pol oscillators using the framework of the impulse sensitivity function (ISF) shows that most of the up-conversion efficiency results from the first harmonic of the ISF, which is not perfectly in quadrature to the output voltage waveform.
Abstract: Harmonic content modulation of the oscillator output voltage can contribute to flicker noise up-conversion in LC-tuned oscillators. The paper reports a quantitative analysis of the effect in Van der Pol oscillators using the framework of the impulse sensitivity function (ISF). It is shown that most of the up-conversion efficiency results from the first harmonic of the ISF, which is not perfectly in quadrature to the output voltage waveform, and from the first harmonic of the transistor current, which is slightly lagging the voltage waveform. A closed-form expression of 1/f3 phase noise in voltage-limited LC-tuned oscillator is derived that is in good agreement with circuit simulations. The paper also shows that the values of both phase shifts are determined by the non-linearity of the active element and are linked to the relevant oscillator parameters, i.e., excess gain and tank quality factor.

41 citations


01 Nov 2012
TL;DR: In this article, a square wave generator using three second generation current conveyers, five resistors and one capacitor with independent control of frequency is presented, which is suitable for very large scale integration (VLSI) implementation.
Abstract: At the outset the foregoing document is represented by square-wave generator using three second generation current conveyers, five resistors and one capacitor with independent control of frequency is presented. The unique features associated with such waveform generator are the easy tunability of frequency over a range of 15 Hz to 150 kHz, extremely low sensitivities as well as suitable for very large scale integration (VLSI) implementation. The working capacity of the proposed circuit is examined with the aid of SPICE models of IC AD 844 AN. Later, the circuit was built with commercially available current feedback operational amplifiers (AD 844 AN), passive components used externally and tested for waveform generation and tunability. Results achieved prove better agreement with the theoretical values. And the non-idealities also are examined.

31 citations


Journal ArticleDOI
TL;DR: In this paper, a smart system for flow measurement is presented, consisting of a micromachined thermal flow sensor combined with a smart front-end electronic interface, based on a novel thermal transduction method, which combines the hot-film and calorimetric sensing principles.
Abstract: A smart system for flow measurement is presented, consisting of a micromachined thermal flow sensor combined with a smart front-end electronic interface. The flow sensor is based on a novel thermal transduction method, which combines the hot-film and calorimetric sensing principles. The sensor consists of four germanium thermistors embedded in a thin membrane and connected to form a Wheatstone bridge supplied with a constant DC current. In this configuration, both the bridge unbalance voltage and the voltage at the bridge supply terminals are functions of the flow offering high initial sensitivity, i.e., near zero flow and wide measurement range, respectively. The front-end interface is based on a CMOS relaxation oscillator circuit where the frequency and the duty cycle of a rectangular-wave output signal are related to the bridge unbalance voltage and the voltage at the bridge supply terminals, respectively. Furthermore, the amplitude of the output signal is a linear function of the operating temperature. In this way, a single output signal advantageously carries two pieces of information related to the flow velocity and provides an additional measurement of the sensor operating temperature, which enables the correction of the temperature dependence of the sensor readouts. The system has been experimentally characterized for the measurement of nitrogen gas flow velocity at different sensor temperatures. The initial sensitivities at room temperature result 13.7 kHz/(m/s) and 23.5%/(m/s), in agreement with FEM simulations, for frequency and duty cycle readouts, respectively, with an equivalent velocity resolution of about 0.5 and 1.3 cm/s.

29 citations


Proceedings ArticleDOI
25 Oct 2012
TL;DR: In this paper, a fast and accurate simulation technique to evaluate the impulse sensitivity function (ISF) of an oscillator is presented, based on the linear-time variant (LTV) analysis of oscillators.
Abstract: This paper presents a fast and accurate simulation technique to evaluate the impulse sensitivity function (ISF) of an oscillator. The proposed method, based on the linear-time variant (LTV) analysis of oscillators, computes the impulse phase response by means of periodic steady-state (PSS) and periodic transfer function (PXF) simulations available in commercial simulators (Spectre, Eldo, etc.). This technique overwhelms the classical simulation method based on transient analysis and injection of charge pulses along the oscillator period in terms of speed, precision and ease of use. The good accuracy of the proposed method has been verified in two oscillator topologies, namely a Van der Pol and a ring oscillator.

23 citations


Journal ArticleDOI
TL;DR: In this paper, an optical and electrical relaxation oscillator making use of an S-shaped negative resistance characteristic of a recently developed light-emitting diode using a bulk silicon crystal homojunction was proposed.
Abstract: We propose an optical and electrical relaxation oscillator making use of an S-shaped negative resistance characteristic of a recently developed light-emitting diode using a bulk silicon crystal homojunction. From simulations, we found that the voltage and optical power oscillated synchronously, and their oscillation frequency increased with increasing injection current. The synchronous oscillation was also confirmed by experimental measurements. The amplitude of the voltage was 50 Vp-p, the amplitude of the optical power was 3 mWp-p, and the maximum oscillation frequency was 34 kHz. The measured value of the spontaneous emission lifetime of a Si wafer was 900 ps, which was as short as that of direct transition-type semiconductors.

20 citations


Journal ArticleDOI
TL;DR: In this article, a dual-chip system for inclination measurement is presented, which consists of a MEMS (microelectromechanical system) piezoresistive accelerometer manufactured in silicon bulk micromachining and a CMOS (complementary metal oxide semiconductor) ASIC (application specific integrated circuit) interface designed for resistive-bridge sensors.
Abstract: In this paper a dual-chip system for inclination measurement is presented. It consists of a MEMS (microelectromechanical system) piezoresistive accelerometer manufactured in silicon bulk micromachining and a CMOS (complementary metal oxide semiconductor) ASIC (application specific integrated circuit) interface designed for resistive-bridge sensors. The sensor is composed of a seismic mass symmetrically suspended by means of four flexure beams that integrate two piezoresistors each to detect the applied static acceleration, which is related to inclination with respect to the gravity vector. The ASIC interface is based on a relaxation oscillator where the frequency and the duty cycle of a rectangular-wave output signal are related to the fractional bridge imbalance and the overall bridge resistance of the sensor, respectively. The latter is a function of temperature; therefore the sensing element itself can be advantageously used to derive information for its own thermal compensation. DC current excitation of the sensor makes the configuration unaffected by wire resistances and parasitic capacitances. Therefore, a modular system results where the sensor can be placed remotely from the electronics without suffering accuracy degradation. The inclination measurement system has been characterized as a function of the applied inclination angle at different temperatures. At room temperature, the experimental sensitivity of the system results in about 148 Hz/g, which corresponds to an angular sensitivity around zero inclination angle of about 2.58 Hz deg−1. This is in agreement with finite element method simulations. The measured output fluctuations at constant temperature determine an equivalent resolution of about 0.1° at midrange. In the temperature range of 25–65 °C the system sensitivity decreases by about 10%, which is less than the variation due to the microsensor alone thanks to thermal compensation provided by the current excitation of the bridge and the positive temperature coefficient of resistance of the piezoresistors.

19 citations


Dissertation
01 Jan 2012
TL;DR: In this paper, the authors describe the reliable design of tunnel diode and resonant tunneling diode (RTD) oscillator circuits, and present a circuit for direct measurement of I-V characteristics.
Abstract: This thesis describes the reliable design of tunnel diode and resonant tunneling diode (RTD) oscillator circuits. The challenges of designing with tunnel diodes and RTDs are explained and new design approaches discussed. The challenges include eliminating DC instability, which often manifests itself as low frequency parasitic oscillations, and increasing the low output power of the oscillator circuits. To stabilise tunnelling devices, a common but sometimes ineffective approach is the use of a resistor of suitable value connected across the device. It is shown in this thesis that this resistor tunnel diode circuit can be described by the Van der Pol model. Based on this model, design equations have been derived which enable the design of current-voltage (I-V) measurement circuits that are free from both low frequency bias oscillations and high frequency parasitic oscillations. In the conventional setup, the I-V characteristic of the tunnelling device is extracted from the measurement by subtracting from the measured current the current through the stabilising resistance at each bias voltage. In this thesis, also using the Van der Pol model, a circuit for the direct measurement of I-V characteristics is proposed. This circuit utilises a series resistor-capacitor combination in parallel with the tunnelling device for stabilisation. Experimental results show that IV characterisation of tunnel diodes in the negative differential resistance (NDR) region free from oscillations can be made. A new test set-up suitable for radio frequency (RF) characterisation of tunnel diodes over the entire NDR region was also developed. Initial measurement results on a packaged tunnel diode indicate that accurate characterisation and subsequent small-signal equivalent circuit model extraction for the NDR region can be done. To address the limitations of low output power of tunnel diode or RTD oscillators, a new multiple device circuit topology, incorporating a novel design methodology for the DC bias decoupling circuit, has been developed. It is based on designing the oscillator specifically for sinusoidal oscillations, and not relaxation oscillations which are also possible in tunnel diode oscillators. The oscillator circuit can also be described by the Van der Pol model which provides theoretical predictions of the maximum inductance, in terms of the tunnel diode device parameters, that is required to resonate with the device capacitance for sinusoidal oscillations. Each of the tunnel diodes in the multiple device oscillator circuit is decoupled from the others at DC and so can be stabilised independently. The oscillator topology uses parallel resonance but with each tunnel diode individually biased and DC decoupled making it possible to employ several tunnel diodes for higher output power. This approach is expected to eliminate parasitic bias oscillations in tunnel diode oscillators whilst increasing the output power of a single oscillator. Simulation and experimental oscillator results were in good agreement, with a two-tunnel diode oscillator exhibiting approximately double the output power as compared to that of a single tunnel diode oscillator, i.e. 3 dB higher. Another method considered for the realisation of higher output power tunnel diode or RTD oscillators was series integration of the NDR devices. A new method to suppress DC instability of the NDR devices connected in series with all the devices biased in their NDR regions was investigated. It was successfully employed for DC characterisation with integrations of 2 and 5 tunnel diodes. Even though no suitable oscillator circuit topology and/or methodology with series-connected NDR devices could be established for single frequency oscillation, the achieved results indicated that this approach may be worthy of further investigation. The final aspect of this project focussed on the monolithic realisation of RTD oscillators. Monolithic oscillators in coplanar waveguide (CPW) technology were successfully fabricated and worked at a fundamental frequency of 17.5 GHz with -21.83 dBm output power. Finally, to assess the potential of RTD oscillators for high frequency signal generation, a theoretical analysis of output power of stabilised RTD oscillators was undertaken. This analysis suggests that it may be possible to realise RTD oscillators with high output power (0 dBm) at millimetre-wave and low terahertz (up to 1 THz) frequencies.

Proceedings ArticleDOI
01 Dec 2012
TL;DR: A fully on-chip CMOS relaxation oscillator (ROSC) with a PVT variation compensation circuit that compensates for comparator's non-idealities caused by offset voltage and delay time is proposed.
Abstract: A fully on-chip CMOS relaxation oscillator (ROSC) with a PVT variation compensation circuit is proposed in this paper. The circuit is based on a conventional ROSC and has a distinctive feature in the compensation circuit that compensates for comparator's non-idealities caused by offset voltage and delay time. We also developed a bias circuit consisting of positive and negative temperature coefficient resistors to obtain the temperature compensated clock frequency. Measurement results demonstrated that the circuit can generate a stable clock frequency of 6.66 kHz. The power dissipation was 940 nW. The measured line regulation and temperature coefficient were 0.98%/V and 56ppm/°C, respectively.

Journal ArticleDOI
TL;DR: It is found that a period mismatch induces better entrainment in both types of oscillator; the enhancement occurs in the vicinity of the bifurcation on their limit cycles.
Abstract: Biological oscillators coordinate individual cellular components so that they function coherently and collectively. They are typically composed of multiple feedback loops, and period mismatch is unavoidable in biological implementations. We investigated the advantageous effect of this period mismatch in terms of a synchronization response to external stimuli. Specifically, we considered two fundamental models of genetic circuits: smooth- and relaxation oscillators. Using phase reduction and Floquet multipliers, we numerically analyzed their entrainability under different coupling strengths and period ratios. We found that a period mismatch induces better entrainment in both types of oscillator; the enhancement occurs in the vicinity of the bifurcation on their limit cycles. In the smooth oscillator, the optimal period ratio for the enhancement coincides with the experimentally observed ratio, which suggests biological exploitation of the period mismatch. Although the origin of multiple feedback loops is often explained as a passive mechanism to ensure robustness against perturbation, we study the active benefits of the period mismatch, which include increasing the efficiency of the genetic oscillators. Our findings show a qualitatively different perspective for both the inherent advantages of multiple loops and their essentiality.

Journal ArticleDOI
TL;DR: This paper presents an original time-domain analysis of the phase-diffusion process, which occurs in oscillators due to the presence of white and colored noise sources, and provides useful design-oriented closed-form expressions of such phenomena.
Abstract: This paper presents an original time-domain analysis of the phase-diffusion process, which occurs in oscillators due to the presence of white and colored noise sources. It is shown that the method supplies realistic quantitative predictions of phase-noise and jitter and provides useful design-oriented closed-form expressions of such phenomena. Analytical expressions and numerical simulations are verified through measurements performed on a relaxation oscillator whose behavior is perturbed by externally controlled noise sources. Copyright © 2011 John Wiley & Sons, Ltd.

DOI
07 Dec 2012
TL;DR: In this paper, a relaxation oscillator based on integrating the diode-switched currents and Schmitt trigger is presented, derived from a known circuit with operational amplifiers where these active elements were replaced by current conveyors.
Abstract: A novel relaxation oscillator based on integrating the diode-switched currents and Schmitt trigger is presented. It is derived from a known circuit with operational amplifiers where these active elements were replaced by current conveyors. The circuit employs only grounded resistances and capacitance and is suitable for high frequency square and triangular signal generation. Its frequency can be linearly and accurately controlled by voltage that is applied to a high-impedance input. Computer simulation with a model of a manufactured conveyor prototype verifies theoretic assumptions.

Proceedings ArticleDOI
20 May 2012
TL;DR: This paper presents a bandgap reference capable of operating at supply voltages below 1V, developed in a 130nm CMOS technology and occupies an active area of 0.0132mm2.
Abstract: This paper presents a bandgap reference capable of operating at supply voltages below 1V. In contrast to the vast majority of bandgap circuits the multiplication of the proportional to absolute temperature voltage is done by a switched capacitor network. Thus a reduced chip area is achieved. As a clock is needed for the switching, a relaxation oscillator is deeply integrated into the circuit. Combined the circuits provide a continuous sub bandgap voltage reference output of 615mV and a clock signal with a frequency of roughly 53kHz. The overall current consumption is 180nA at room temperature. The circuit is developed in a 130nm CMOS technology and occupies an active area of 0.0132mm2

Proceedings ArticleDOI
01 Dec 2012
TL;DR: The design, analysis, and experimental results of the circuit and its application to a sol gel thin film porous γ-Al2O3 based humidity sensor confirm the theoretical value predicted and have the potential for remotely monitoring measurement parameters accurately.
Abstract: A simple signal conditioning circuit for converting capacitance change into frequency for capacitive humidity sensors is presented. It is based on a relaxation oscillator in which output frequency is linearly related to the capacitive unbalance of an active bridge. The design, analysis, and experimental results of the circuit and its application to a sol gel thin film porous γ-Al 2 O 3 based humidity sensor are reported. Experimental results confirm the theoretical value predicted. The circuit covering wide capacitance measurement range has the potential for remotely monitoring measurement parameters accurately.

Patent
12 Sep 2012
TL;DR: In this article, a relaxation oscillator with a low temperature drift characteristic and a debug method of a current adjusting mode is combined, such that monolithic integration of the relaxation oscillators is realized while the oscillation frequency of the oscillator obtains excellent temperature stability.
Abstract: The invention provides a relaxation oscillator with a low temperature drift characteristic and a debug method thereof, and relates to an oscillator field. The oscillator circuit comprises a bias module, a register and an oscillation module. The oscillation module is composed of a switching structural circuit, a comparator and a capacitor charging and discharging circuit. The oscillator uses switching structural circuit as a core, and a debug method of a current adjusting mode is combined, such that monolithic integration of the relaxation oscillator is realized while the oscillation frequency of the oscillator obtains excellent temperature stability. The disclosed switching structural circuit in the invention is provided for enable the relaxation oscillator to acquire the good temperature stability. According to a working principle of the circuit, the relaxation oscillator always possesses the good temperature stability no matter threshold voltages with different temperature characteristics are provided to the comparator by components in the switching structural circuit. The relaxation oscillator with the low temperature characteristic in the invention and the debug method thereof are suitable for any standard CMOS technologies.

Patent
14 Mar 2012
TL;DR: In this paper, a relaxation oscillator with low power consumption was proposed, where a current source generation circuit, a charge and discharge circuit, and a delay circuit are used to solve problems like high power consumption and the like.
Abstract: The invention relates to a relaxation oscillator with low power consumption, wherein the relaxation oscillator is invented for solving problems like high power consumption and the like in the prior art. The relaxation oscillator comprises a current source generation circuit, a charge and discharge circuit and a delay circuit. The current source generation circuit utilizes a cross voltage formed by connection of a gate and a drain of a first transistor so as to enable a resistor to generate a bias current; the charge and discharge circuits utilize a mirroring current of the bias current to enable a capacitance to be charged, so that a second transistor that has the same characteristics as the first transistor to be conducted; and with utilization of the delay circuit that is connected between a drain of the second transistor and a gate of a third transistor, the capacitance is able to be charged and discharged periodically, so that an oscillation frequency that is independent of a power source voltage is generated and a low power consumption effect is realized.

Patent
Peter Busch1
29 May 2012
TL;DR: In this paper, a switch-on and switch-off time for a switched-mode power supply unit for a computer includes at least one switching element that switches a charging current to charge a storage element, a secondary output circuit that provides an output voltage (Vout+), and a controllable oscillator circuit that provided a switching clock.
Abstract: A switched-mode power supply unit for a computer includes at least one switching element that switches a charging current to charge a storage element, at least one secondary output circuit that provides an output voltage (Vout+), at least one controllable oscillator circuit that provides a switching clock, and at least one control circuit that determines a switch-off time for the at least one switching element, wherein, in operation of the switched-mode power supply unit, a mean oscillator clock of the oscillator circuit is controlled in dependence on a controlled variable (Vcontrol) specifying the output voltage or power of the secondary output circuit such that the mean oscillator clock rises monotonously with the output power and a switch-on time for the at least one switching element is determined in dependence on the mean oscillator clock and a random deviation.

Journal ArticleDOI
TL;DR: This paper presents the class-EM oscillator with the second-harmonic injection current, along with its design procedure, design curves, and design example, which denotes the validity of the design procedure.
Abstract: This paper presents the class-EM oscillator with the second-harmonic injection current, along with its design procedure, design curves, and design example. In the proposed oscillator, the output frequency of the proposed oscillator is locked with the input frequency of the injection circuit. Additionally, the switch-voltage and switch-current waveforms in the main circuit achieve the class-EM zero-voltage switching, zero-voltage-derivative switching, zero-current switching, and zero-current-derivative switching (ZVS/ZVDS/ZCS/ZCDS) conditions and the switch voltage waveform in the injection circuit satisfied the class-E ZVS/ZDS conditions. In the laboratory experiment, the oscillator achieved 92.0% power-conversion efficiency at 34.8 W output power and 1 MHz operating frequency. The experimental results agreed with the numerical predictions quantitatively, which denotes the validity of the design procedure.

Proceedings ArticleDOI
01 Nov 2012
TL;DR: This paper presents two memristor-based relaxation oscillators that can be fully integrated on-chip giving an area-efficient solution and give higher frequency other than the existing reactance-less oscillator and provide a wider range of the resistance.
Abstract: This paper presents two memristor-based relaxation oscillators. The proposed oscillators are designed without the need of any reactive elements, i.e., capacitor or inductor. As the "resistance storage" property of the memristor can be exploited to generate the oscillation. The proposed oscillators have the advantage that they can be fully integrated on-chip giving an area-efficient solution. Furthermore, these oscillators give higher frequency other than the existing reactance-less oscillator and provide a wider range of the resistance. The concept of operation and the mathematical analysis for the proposed oscillators are explained and verified with circuit simulations showing an excellent agreement.

Proceedings ArticleDOI
12 Nov 2012
TL;DR: The design of an area-efficient CMOS relaxation oscillator for low power applications is described, which includes a temperature compensation scheme based on the matching of bias current circuit and oscillator inverters threshold voltages that provides a clock frequency stable over the entire temperature range.
Abstract: The design of an area-efficient CMOS relaxation oscillator for low power applications is described. Its architecture includes a temperature compensation scheme based on the matching of bias current circuit and oscillator inverters threshold voltages that provides a clock frequency stable over the entire temperature range (−40µ C∼ 125µ C). The circuit is the auto-wakeup IP core of a microcontroller family for consumer applications, occupies an area of 0.03mm2 in a 0.5µm CMOS process, operates from 1.5V to 5.5V, and consumes 800nA.

Patent
24 Jul 2012
TL;DR: In this paper, a reference circuit, an oscillator architecture that includes the reference circuit and a method for operating the reference circuits is described, which includes a voltage reference generator and a current reference generator.
Abstract: A reference circuit, an oscillator architecture that includes the reference circuit and a method for operating the reference circuit are described. In one embodiment, the reference circuit includes a voltage reference generator configured to generate a reference voltage and a current reference generator configured to generate a reference current based on the reference voltage. The current reference generator includes a level shifter circuit configured to generate intermediate voltages based on the reference voltage, a first current reference circuit configured to generate intermediate currents based on the intermediate voltages, where the intermediate currents are correlated to the reference voltage, and a second current reference circuit configured to combine the intermediate currents to generate the reference current. Other embodiments are also described.

Patent
07 Sep 2012
TL;DR: In this paper, a sensor interface circuit is provided for resolving sensor signals from a plurality of sensors into a digital sensor signal, the circuit consists of a relaxation oscillator for receiving and pre-processing the sensor signals to generate an analog sensor signal.
Abstract: A sensor interface circuit is provided for resolving sensor signals from a plurality of sensors into a digital sensor signal, the sensor interface circuit comprising: a relaxation oscillator for receiving and pre-processing the sensor signals to generate an analog sensor signal, the relaxation oscillator comprising one or more dynamic circuits; and a monitoring module for receiving the analog sensor signal and generating the digital sensor signal in response thereto. There is also provided a sensor system front-end and a relaxation oscillator.

Proceedings Article
21 May 2012
TL;DR: This paper presents a novel and simple simulation method, based on the linear-time variant (LTV) analysis of oscillators, that computes the phase response in the frequency domain and overwhelms the classical simulation method based on transient analysis and injection of charge pulses along the oscillator period.
Abstract: This paper presents a novel and simple simulation method to evaluate the impulse phase response of an oscillator. The technique, based on the linear-time variant (LTV) analysis of oscillators, computes the phase response in the frequency domain. It can be performed by means of periodic steady-state (PSS) and periodic transfer function (PXF) simulations available in commercial simulators (Spectre, Eldo, etc.). This method overwhelms the classical simulation method based on transient analysis and injection of charge pulses along the oscillator period in terms of both speed and precision. The good accuracy of the frequency domain method has been verified in two practical case studies, evaluating the 1/f3 phase noise in a classical Van der Pol oscillator and estimating the injection locking range in a ring oscillator-based frequency divider.

Patent
01 Nov 2012
TL;DR: In this article, a reconfigurable element based on nonlinear (chaotic) dynamics is adapted to implement the three different multivibrator configurations (monostable, astable, and bistable).
Abstract: A reconfigurable element based on nonlinear (chaotic) dynamics is adapted to implement the three different multivibrator configurations. A nonlinear dynamical system, under parameter modulating control, operates as a tunable oscillator with different dynamical regimes which in turn provide the different multivibrator configurations (monostable, astable, and bistable). The reconfigurable multivibrator is realized as a tunable circuit which includes an input stage for receiving at least one input voltage signal and an output stage that produces a digital two-level electric output signal. The all-in-one reconfigurable multivibrator device consisting of a nonlinear oscillator circuit electrically coupled to the input/output circuitry is used in at least, but not limited to three basic applications, namely, an irregular width pulse generator, a rising flank trigger and a full RS flip-flop device.

Journal ArticleDOI
TL;DR: In this article, a wireless sensor readout circuit for continuous physiological parameters monitoring including a potentiostat, a data generation unit and a frequency-shift-keying (FSK) modulator unit with the low dropout (LDO) regulator for biomedical implant system is presented.
Abstract: This paper reports a wireless sensor readout circuit for continuous physiological parameters monitoring including a potentiostat, a data generation unit and a frequency-shift-keying (FSK) modulator unit with the low drop-out (LDO) regulator for biomedical implant system. The potentiostat can generate an output potential of 0.7 V for the data generation unit. The data generation unit is designed based on a relaxation oscillator scheme and can be used to sense a current signal from any amperometric biomedical sensor and convert the signal to a square waveform in which the frequency of the square wave signal is proportional to the sensor current. FSK modulation scheme has been selected for wireless transmission. Designed with a very simple ring oscillator, this modulator integrates the modulation functionality into the oscillator itself by using the data signal to control the oscillation frequency. The prototype circuits have been fabricated in a 0.35 μm bulk complementary metal-oxide semiconductor (CMOS) process. Working with a regulated 1.8 V supply, the potentiostat consumes only 2 μA of current while the data generation unit can generate around 15.7 kHz output frequency with an input current of 1 μA. The FSK modulator consumes a total current of around 19 μA for a carrier frequency around 1 MHz. An off-chip demodulator is constructed to demodulate the data signal from the FSK modulator and the demodulated signal has less than 1.6 % variation of frequency.

Patent
05 Dec 2012
TL;DR: In this article, a negative feedback loop is proposed to accurately control the delay of a comparator so as to replace the traditional method of reducing the delay by increasing the power consumption.
Abstract: The invention discloses a relaxation oscillator with low power consumption. In order to overcome the shortcomings of uncertain transmission delay, low precision of the oscillating frequency, and poor temperature stability in the relaxation oscillator, the invention provides a method of a feedback control; by detecting the output frequency of the relaxation oscillator or the change of a signal value when the charging period of a regular capacitor is ended, a negative feedback loop is structured to accurately control the delay of a comparator so as to replace the traditional method of reducing the delay by increasing the power consumption, therefore, the power consumption is reduced; and meanwhile, the precision of the oscillating frequency and the temperature stability are improved.

Patent
04 Oct 2012
TL;DR: In this paper, a single capacitive element, a single current source and a switching network are utilized for CMOS relaxation oscillators, which allows both nodes of the capacitive elements to rise and fall between a positive and a negative voltage with respect to ground supply, without causing leakage to substrate or risk of latch-up.
Abstract: Methods and circuits for CMOS relaxation oscillators are disclosed. A single capacitive element, a single current source and a switching network are utilized. A switching network of the oscillator allows both nodes of the capacitive element to rise and fall between a positive and a negative voltage with respect to ground supply, without causing leakage to substrate or risk of latch-up, i.e. the inadvertent creation of a low-impedance path. The oscillator requires minimum silicon area, has an improved duty cycle, is particular useful for implementing lower frequency clocks and is enabled for smaller technology nodes, lower than 250 nm, due to lower supply voltage.