Showing papers on "Subthreshold conduction published in 1994"

Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures

Abstract: Flicker noise is the dominant noise source in silicon MOSFET's. Even though considerable amount of work has been done in investigating the noise mechanism, controversy still exists as to the noise origin. In this paper, a systematic study of flicker noise in CMOS transistors from twelve different fabricators is reported under various bias conditions corresponding to the gate voltage changing from subthreshold to strong inversion, and the drain voltage changing from linear to saturation regions of operation. The measurement temperature was varied from room temperature down to 5 K. Experimental results consistently suggest that 1/f noise in n-channel devices is dominated by carrier-density fluctuation while in p-channel devices the noise is mainly due to mobility fluctuation. >

Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation

Abstract: A dynamic threshold voltage IGFET such as a MOSFET is operable at voltages of 0.6 volt or less. The threshold voltage of the transistor is reduced to zero volt or less by interconnecting the gate contact and the device body in which the voltage controlled channel is located. Several efficient connections using through hole plating or polycrystalline silicon gate extension are disclosed. A higher power supply voltage can be used by interconnecting the gate and device body through a smaller MOSFET.

0.05-μm-Gate InAlAs/InGaAs High Electron Mobility Transistor and Reduction of Its Short-Channel Effects

Abstract: In this paper, we discusse the advantages of thinning the channel on short-channel effects for lattice-matched InAlAs/InGaAs high electron mobility transistors (HEMTs) with sub-0.1-µm-long gates with regard to the performance of a 0.05-µm-gate device. To fabricate a sub-0.1-µm gate, the opening shape of the gate-footprint is controlled by using a bilayer dielectric film system and RIE side etching. The device shows a current gain cutoff frequency of 300 GHz and g m/g d ratio of 15. Thinning the channel and the barrier down to 100 A improves carrier confinement and subthreshold characteristics and is indispensable for reducing the short-channel effects in the sub-0.1-µm-gate-length region.

Characterization of subthreshold MOS mismatch in transistors for VLSI systems

Abstract: MOS transistor mismatch is revisited in the context of subthreshold operation and VLSI systems. We report experimental measurements from large transistor arrays with device sizes typical for digital and analog VLSI systems (areas between 9 and 400μm2). These are fabricated at different production qualified facilities in 40-nm gate oxide,n-well andp-well, mask lithography processes. Within the small area of our test-strips (3 mm2), transistor mismatch can be classified into four categories: random variations, “edge,” “striation,” and “gradient” effects. The edge effect manifests itself as a dependence of the transistor current on its position with reference to the surrounding structures. Contrary to what was previously believed, edge effects extend beyond the outer most devices in the array. The striation effect exhibits itself as a position-dependent variation in transistor current following a sinusoidal oscillation in space of slowly varying frequency. The gradient effect is also a position-dependent spatial variation but of much lower frequency. When systematic effects are removed from the data, the random variations follow an inverse linear dependence on the square root of transistor area.

Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's

Abstract: We derived a simple formula for the subthreshold swing S in double-gate (DG) SOI MOSFET's. Our formula, which depends only on a scaling device parameter, matches the device simulation results. From these results, our equations are simple and give a scaling rule for DG-SOI MOSFET's. >

Trends in low-power RAM circuit technologies

Abstract: Trends in low-power RAM circuit technologies are reviewed. The following provide major contribution to power reduction: lowering operating voltage by lowering the external supply voltage, half-V/sub DD/ data-line precharging and on-chip voltage down converting; reducing charging capacitance through partial activation of multi-divided array, and CMOS NAND decoder; reducing DC current through partial activation of multi-divided word line and pulsed operations of periphery using address transition detection. These contributions have made possible a DRAM active power reduction of as much as 2 to 3 orders of magnitude over the last decade. Moreover, MOS transistor subthreshold current reduction circuits such as source-gate backbiasing scheme, which are essential in an ultra-low voltage era, might reduce an active current of a 1-V 16Gb DRAM from 1.2 A down to 22 mA.

Analytical surface potential expression for thin-film double-gate SOI MOSFETs

Abstract: Using a perturbation theory, we derived an analytical surface potential expression for subthreshold and strong-inversion regions. This enabled us to derive analytical models for the subthreshold slope, threshold voltage, and induced electron concentration of a double-gate SOI MOSFET. We also clarified the dependence of the device characteristics on device parameters, and explained the ideal subthreshold factor. We do not expect volume inversion in practical devices. Our models' predictions agree well with numerical and experimental data.

Subthreshold-current reduction circuits for multi-gigabit DRAM's

Abstract: Two subthreshold-current reduction circuit schemes are described to suppress the increase in current in multi-gigabit DRAM's. One is a hierarchical power-line scheme for iterative circuits. In this scheme, a group of circuits is divided into blocks; only the selected block is supplied with power, while the subthreshold current to the many nonselected blocks is reduced. This scheme minimizes the number of circuits carrying the large subthreshold current. Applications of this scheme to word drivers, decoders and sense-amplifier driving circuits are shown. The other scheme is a switched-power-supply inverter with a level holder for random combinational logic circuits. In the active mode of the chip, the operating period of the inverter is distinguished from the inactive period. The inverter is supplied with power only in the operating period, while in the inactive period the subthreshold current is shut off and the output level is kept by the flip-flop level holder. This scheme shortens the period in which the large subthreshold current flows. Both schemes are evaluated for a conceptually-designed 16-Gb DRAM. They reduce its active current by ten-fold from the conventional 1.2 A to 116 mA. >

A novel Silicon-On-Insulator (SOI) MOSFET for ultra low voltage operation

Abstract: To extend the lower bound of power supply voltage, we propose a variable threshold voltage MOSFET (VTMOS) built on silicon-on-insulator (SOI). Threshold voltage of VTMOS drops as gate voltage is raised, resulting in a much higher current drive than regular MOSEET, at low Vdd. On the other hand, V/sub t/ is high at V/sub gs/=O, thus the leakage current is low. The SOI devices used in the study were built on SIMOX wafers. A four terminal layout was used to provide separate source, drain, gate, and body contacts.

Interface characterization of fully-depleted SOI MOSFET by a subthreshold I-V method

Abstract: Interface state densities can dramatically affect the performances of MOSFETs by causing threshold voltage shift and mobility degradation. In SOI structures, due to the complex multi-interface nature and small gate area, the interface state characterization still remains a very challenging problem. Conventional C-V method is not suitable for investigating interfaces in SOI MOS devices, mainly because of the large area needed and the high series resistance in thin-film. Several other measurement techniques based on currents rather than capacitance have been proposed. In this work, an evolved technique for characterizing interface state density in fully-depleted SOI MOSFETs is presented. By measuring subthreshold swing of the SOI MOSFETs, the interface state density can be determined. The distribution of both front- and back-interface state densities in the bandgap can be evaluated by applying a rigorous one-dimensional analytical model for FD-SOI MOSFETs operating in the weak inversion regime. In addition, this technique has been applied successfully to the comparison of interface qualities of various SOI wafers and the study of electrical stress effect. The SOI devices used in this study were n-channel and p-channel MOSFETs fabricated with submicron CMOS technology on both SIMOX and Bonded-and-Etchback SOI (BESOI) wafers.

Subthreshold slope of long-channel accumulation-mode p-channel SOI MOSFETs

Abstract: An analytical model for the subthreshold slope of the accumulation-mode p-channeI SOI MOSFET is developed. The exact solution of the equations reveals that the subthreshold swing is slightly larger (by a few percent) than that of enhancement (inversion-mode) fully depleted SOI devices. In most cases, however, the classical subthreshold slope expression developed for inversion-mode fully depleted SOI MOSFET can be used as a good approximation for accumulation-mode devices, which means that the subthreshoId swing tends to the ideal value of S-0 = kT/q 1n(10) mV/dec if the buried oxide is sufficiently thick and if the interface trap density is sufficiently low.

Density of Deep Bandgap States in Amorphous Silicon From the Temperature Dependence of Thin Film Transistor Current

Abstract: We have measured the current-voltage characteristics of amorphous silicon thin film transistors (a-Si TFTs) over a wide range of temperatures (20 to 160°C) and determined the activation energy of the channel current as a function of gate bias with emphasis on the leakage current and subthreshold regimes. We propose a new method for estimating the density of localized states (DOS) from the dependence of the derivative of activation energy with respect to gate bias. This differential technique does not require knowledge of the flat-band voltage (V FB) and does not incorporate integration over gate bias. Using this Method, we have characterized the density of localized states with energies in the range 0.15–1.2 eV from the bottom of the conduction band and have found a wide peak in the DOS in the range of 0.8–0.95 eV below the conduction band. We have also observed that the DOS peak in the lower half of the bandgap increases in magnitude and shifts towards the conduction band as a result of thermal and bias stress. We also measured an overall increase in the DOS in the upper half of the energy gap and an additional peak, centered at 0.2 eV below the conduction band, which appear due to the applied stress. These results are in qualitative agreement with the defect pool Model [1,2].

Method for fabricating insulated gate field effect transistor having subthreshold swing

Abstract: Insulated gate field effect transistors (10, 70) having process steps for setting the VT and a device leakage current which are decoupled from the process steps for providing punchthrough protection, thereby lowering a subthreshold swing. In a unilateral transistor (10), a portion (37, 45) of a dopant layer (25, 30) between a source region (48, 51) and a drain region (49, 52) serves as a channel region and sets the VT and the device leakage current. A halo region (34, 39) contains the source region (48, 51) and sets the punchthrough voltage. In a bilateral transistor (70), both a source region (83, 86) and a drain region (84, 87) are contained within halo regions (75, 74, 79, 81). A portion (76, 82) of a dopant layer (25, 30) sets the VT and a leakage current, whereas the halo region (75, 79) sets the punchthrough voltage.

A 48,000 pixel, 590,000 transistor silicon retina in current-mode subthreshold CMOS

Abstract: A second generation, contrast sensitive silicon retina is reported in this paper. The architecture and organization is inspired by the outer plexiform processing in the vertebrate retina. Current-mode subthreshold MOS design techniques are employed to obtain high performance and energetic efficiency. The system has been fabricated with 230/spl times/210 pixels on a 1/spl times/1 cm die in a 1.2 /spl mu/m n-well double metal, double poly, digital oriented CMOS technology. The chip incorporates 590,000 transistors, 48,000 pixels, operating in subthreshold/transition region with power dissipation of 50 mW when powered from a 5 V power supply. The pixel has a frequency response of 100 kHz.

A Gaussian synapse circuit for analog VLSI neural networks

Abstract: Back-propagation neural networks with Gaussian function synapses have a better convergence property over those with linear-multiplying synapses. A compact analog Gaussian synapse cell which is not biased in the subthreshold region has been designed for fully-parallel operation. This cell can approximate a Gaussian function with accuracy around 98% in the ideal case. Device mismatch induced by fabrication process will cause some degradation to this approximation. Programmability of the proposed Gaussian synapse cell is achieved by changing the stored synapse weight W/sub ji/, the reference current and the sizes of transistors in the differential pair. >

Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's

Abstract: A two-dimensional power-line selection scheme for an iterative CMOS circuit block is proposed to reduce the subthreshold current. In this scheme, a block is divided into sub-blocks in a two-dimensional arrangement and selectively energized by two-dimensional power-line selection. It is shown to be suitable for dual word-line structure, particularly because of its single sub-word line activation. This scheme achieves a very large reduction of active current to one sixteenth, from 116 mA to 22 mA for a 1-V 16-Gb DRAM with dual word-line structure, while maintaining a speed comparable to existing multi-megabit DRAM's. The proposed scheme is promising for reducing the active power of future multi-gigabit DRAM's. >

Subthreshold rectification in neostriatal spiny projection neurons.

Abstract: Intracellular recordings from slice preparations were used to assess the subthreshold electrophysiological behavior of rat neostriatal projection neurons. Both current steps and ramp currents were used to estimate the current-voltage relationship (I–V plot). Inward rectification in the subthreshold range was a characteristic of most neurons. The amount of rectification varied greatly, and it was complex: membrane voltage trajectories in response to ramps were made up by almost piecewise changes in the rate of voltage rise, suggesting that multiple conductances contribute to the subthreshold range. Inward current blockers such as tetrodotoxin (TTX) or Cd2+ decreased inward rectification, whereas outward current blockers such as tetraethylammonium (TEA) or 4-aminopyridine (4-AP) increased inward rectification. However, most inward rectification was due to TEA- and Cs+-sensitive conductances and not to TTX- or Cd2+-sensitive conductances. Cs+-sensitive conductances predominated at more negative membrane potentials, whereas 4-AP-sensitive conductances predominated at just ±10 mV below the firing threshold. In spite of a very slow activation, there was evidence for transient outward currents modulating the response, i.e., 4-AP-sensitivity, and voltage-sensitivity for firing frequency and threshold. TEA-sensitive conductances also contributed toward fixing the firing threshold. These results imply the contribution of various ion conductances on the shaping of the characteristic physiological firing recorded in vivo. Modulation of these responses by transmitters or peptides may help to understand neural processing in the neostriatum.

Short channel models and scaling limits of SOI and bulk MOSFETs

Abstract: Analytical device-physics-based models for subthreshold drain current in short channel SOI MOSFETs facilitate accurate and efficient circuit simulation. These models also enable prediction of device scaling limits determined by subthreshold conduction and comparison of these limits with bulk MOSFETs for the same threshold and supply voltages. >

Method for electrically characterizing the insulator in SOI devices

Abstract: A rapid method for determining electrical characteristics of SOI wafers whereby the silicon substrate acts as a gate and tungsten probes make a source and drain connection at the top silicon surface to form a point contact transistor. Drain current is measured as a function of gate voltage as gate voltage is swept from negative to positive values. The subthreshold voltage current characteristic exhibits a minimum drain current occurring close to zero gate voltage. The tungsten probe point contacts apparently are responding to both electron and hole conduction or simply intrinsic CMOS behavior. Using current voltage characteristics, estimates may be made of interface state density and oxide charge density. Analysis of the gate voltage shift for minimum drain current allows determination of threshold voltage shift due to radiation.

Two-dimensional metal-semiconductor field effect transistor for ultra low power circuit applications

Abstract: We describe a novel 2-dimensional metal-semiconductor field effect transistor (2-D MESFET) in which opposing Schottky side gates formed on the sidewall of a modulation-doped AlGaAs-InGaAs heterostructure modulate the channel width and the drain current. The drain current ranged from 0 to 210 /spl mu/A and the maximum measured transconductance was 212 /spl mu/S (212 mS/mm) at room temperature for a 1/spl times/1 micron channel. The threshold voltage was -0.45 V and the subthreshold ideality factor was 1.30. The estimated gate capacitance was 0.8 fF//spl mu/m, or about half the equivalent capacitance of conventional HFET's. The cutoff frequency f/sub T/ was estimated to be 21 GHz. The narrow channel effect, which limits the minimum power consumption in conventional FET's, is practically eliminated in this device. >

Subthreshold frequency selectivity in avian auditory thalamus

Abstract: 1. We studied the frequency responses of neurons in the nucleus ovoidalis (OV), the principal thalamic auditory relay nucleus of the chicken, in the subthreshold range of membrane potentials. The frequency response is the impedance amplitude profile evident in the voltage response to a broadband stimulus. The stimulus was a deterministic periodic current input of small amplitude, sweeping through a specified frequency range. We used whole-cell, tight-seal recording techniques in slices to study the voltage responses and membrane properties in current and voltage clamp. 2. Generally, low-frequency resonant humps with peak impedances of approximately 6 Hz characterized the frequency responses of OV neurons. This resonance was the principal determinant for frequency selectivity in the majority of OV neurons expressing only a tonic mode of firing. 3. The 6-Hz resonance was voltage dependent and most distinct where the activation ranges of a hyperpolarization activated inward current (IH) and a persistent Na+ current tend to overlap. The potential range for optimal resonance often included the resting potential. 4. Application of the Na+ current antagonist, tetrodotoxin, blocked the persistent Na+ current and most of the resonant hump at depolarized levels but did not affect the resonant peak along the frequency axis. Thus the persistent Na+ current may serve to amplify the resonance. 5. Extracellular application of Cs+, but not Ba2+, blocked a voltage sag during pulsed hyperpolarization as well as the IH current. Application of Cs+ also eliminated the 6-Hz resonance. An IH seems, therefore, instrumental for the resonance. 6. A minority of neurons that expressed low-threshold Ca2+ spikes and burst firing at hyperpolarized states displayed voltage oscillations at 2-4 Hz, spontaneously or in response to pulsatile stimuli. Application of Ni2+ blocked the oscillations and the low-threshold spikes, presumably produced by a T-type Ca2+ current. The resonance at 6 Hz, however, was only slightly affected by Ni2+. A T-type current, therefore, is critical for the 2- to 4-Hz oscillations. 7. Membrane resonance may dominate the power spectrum of subthreshold potential fluctuations. The resonance demonstrated in vitro may be stabilized by experimental procedures; its frequency may be different and more variable in vivo. Resonances in thalamic neurons may play a role in auditory signal processing in birds.

Semiconductor device, and its manufacture

Abstract: PURPOSE:To improve subthreshold property, in a vertical transistor high in integration degree. CONSTITUTION:An opening 16 for a transistor, which pierces this, is provided in an interlayer insulating film 15, and therein epitaxial layers 18 and 19a and 19b to serve as a source/channel/drain are stacked to make an active region 17, and further an opening 20 for a gate electrode, which pierces two layers, is made from above this active layer 17, and herein a gate electrode 23 is made through a gate insulating film 22.

A complete radiation reliability software simulator

Abstract: In this paper we describe a simulator which can be used to study the effects on circuit behavior of two radiation phenomena: single event upset (SEU) and total-dose radiation effects. Using this simulator the user can predict the error rate in large circuits due to single event upset. The error rate model described here uses a well established methodology, but for the first time a different choice is made on picking up the sensitive nodes, enabling a quick prediction even for very complex circuits. The simulator predicts circuit behavior after total-dose irradiation using as inputs: the dose rate and the total dose. Parameter sets that characterize the transistor response to radiation. And the circuit netlist. The total-dose simulator is based on physical models of the changes in the MOSFET caused by radiation. We quantify the degradation of each MOSFET in a circuit with two parameters and determine the change in the MOSFET characteristics-from preirradiation MOSFET data. Using the "irradiated" MOSFET parameters. We can simulate circuit behavior using an ordinary circuit simulator such as SPICE. With this simulator, one can study how resistant a circuit is to changes due to irradiation and design circuits to be functionally radiation "hard" The "double-kink" in the MOSFET subthreshold region due to the parasitic effect of the edge transistors can be simulated and the user is advised when leakage current is unacceptably large. The speed degradation of a ring oscillator was simulated and the results compared with actual measured data. >

Binaural source localizer chip using subthreshold analog CMOS

Abstract: This article describes a chip that identifies the azimuthal location of a sound source using the arrival time difference at two separated microphones. Its circuits are modeled on certain aspects of auditory neurobiology, and attempt to base the location precept on the arrival time difference of the first wavefront in order to function in echoic environments as well as free field situations, The chip contains approximately 50000 transistors, mostly operating in the subthreshold analog mode. It was fabricated on a 4.6 mm/spl times/6.8 mm die a standard 2-micron, p-well CMOS process through MOSIS. >

Gain and noise in subthreshold longitudinal laser modes

Abstract: A theoretical study is presented of the gain profile and noise spectrum in the vicinity of the longitudinal-mode frequency separation of a single-mode laser amplifier of class A or class B. The gain and the noise are associated with the adjacent subthreshold modes on either side of the lasing mode; coupled equations of motion for these three modes have been solved. The amplitudes of the contributions of each individual subthreshold mode to both the gain and the noise are generally anticorrelated. Thus striking cancellation effects should occur in self-heterodyne measurements from the superposition of these contributions. The theoretical predictions are compared with the results of a parallel experimental study on a single-mode argon-ion laser amplifier. Measurements of the gain profiles and noise spectra close to the longitudinal-mode separation are reported for a range of laser output powers. Results are presented for simultaneous detection of the contributions of the two adjacent modes; for detection of only one adjacent mode, the other being suppressed with a Fabry-P\'erot \'etalon; and again for detection of both modes but with their phase relative to the central laser beam modified by a Fabry-P\'erot phase shifter. The predicted cancellation effects are clearly confirmed, and the gain profiles and noise spectra are in good agreement with the theoretical expressions. The noise-cancellation effect is demonstrated by the generation of an optical ``antinoise'' beam that is nearly 180\ifmmode^\circ\else\textdegree\fi{} out of phase with respect to a broadband noisy input beam.

An SOS MOSFET model based on calculation of the surface potential

Abstract: A circuit simulation model is presented suitable for the design of analogue and digital SOS MOSFET integrated circuits. Both the drift and diffusion components of channel current are modeled, which are computed from the surface potentials at the drain and source ends of the channel. The surface potential function varies continuously from subthreshold to strong inversion allowing a smooth transition of device conductances and capacitances at the threshold voltage. Charge is conserved in the model formulation yielding reliable simulation results in transient analysis. The model has been implemented in the SPICE program, together with important extrinsic elements such as impact ionization current, pn-junction current and capacitances, and substrate resistance. The pn-junction current expression includes a physical formulation for the drain leakage current. The influence of temperature on device characteristics is included, making the model valid from /spl minus/55 to 125/spl deg/C. Simulation results are compared with measured dc device characteristics showing considerable improvement over bulk MOS models in predicting the drain conductance. In subthreshold, the model predicts the observed increase in inverse subthreshold slope with drain bias for n-channel devices. Transient simulations show that capacitive coupling from drain, gate and source nodes can strongly influence the floating substrate potential. The model has been successfully applied to the design of analogue SOS circuits. >

Analog circuit for solving assignment problems

Abstract: A novel analog electronic circuit for solving assignment problems is presented. Total length of wiring in the proposed circuit amounts to at most O(n/sup 2/) with n being the number of variables in contrast to O(n/sup 4/) required for previously developed circuits based on the Hopfield neural networks. Moreover, its power dissipation is extremely small by virtue of subthreshold operation of MOS transistors. >

MOSFET threshold extraction from voltage-only measurements

Abstract: The authors describe a method for determining the MOS transistor parameters from voltage measurements by considering two transistors in series. The voltage characteristics at the intermediate node of the two connected transistors allow easy and direct determination of the threshold voltage, the pinch-off voltage and the slope factor. >

Modeling the I-V characteristics of fully-depleted SOI MOSFETs including self-heating

Abstract: Fully-depleted Silicon-On-Insulator (SOI) MOSFETs are a strong potential candidate for future ULSI CMOS applications. In order to evaluate the merits of these devices an accurate model of the output characteristics applicable to sub-half micron channel lengths is needed. Previous work on modeling the I-V (current-voltage) characteristics of thin-film SOI MOSFETs has mainly been based on inaccurate velocity-field relation for carriers in the channel region. Moreover, in most models, conductance and capacitances show discontinuities at the transition points from subthreshold to saturation to linear regions. In this paper we report a physically based continuous analytical model for SOI MOSFETs that is represented by a single drain current equation valid in all regions of device operation ofinterest.

The effects of ionizing radiation on commercial power MOSFETs operated at cryogenic temperatures

Abstract: This is the first report of commercial n- and p-channel power MOSFETs exposed to ionizing radiation while operating in a cryogenic environment. The transistors were exposed to low energy X-rays while placed in a liquid nitrogen-cooled dewar. Results demonstrate significant performance and survivability advantages for space-borne power MOSFETs operated at cryogenic temperatures. The key advantages for low-temperature operation of power MOSFET's in an ionizing radiation environment are: (1) steeper subthreshold current slope before and after irradiation; (2) lower off-state leakage currents before and after irradiation; and (3) larger prerad threshold voltage for n-channel devices. The first two points are also beneficial for devices that are not irradiated, but the advantages are more significant in radiation environments. The third point is only an advantage for commercial devices operated in radiation environments. Results also demonstrate that commercial off-the-shelf power MOSFETs can be used for low-temperature operation in a limited total dose environment (i.e., many space applications). >