Showing papers on "Switched capacitor published in 2004"

A very low power CMOS mixed-signal IC for implantable pacemaker applications

Abstract: Low power consumption is crucial for medical implant devices. A single-chip, very-low-power interface IC used in implantable pacemaker systems is presented. It contains amplifiers, filters, ADCs, battery management system, voltage multipliers, high voltage pulse generators, programmable logic and timing control. A few circuit techniques are proposed to achieve nanopower circuit operations within submicron CMOS process. Subthreshold transistor designs and switched-capacitor circuits are widely used. The 200 k transistor IC occupies 49 mm/sup 2/, is fabricated in a 0.5-/spl mu/m two-poly three-metal multi-V/sub t/ process, and consumes 8 /spl mu/W.

A 1-V 140-/spl mu/W 88-dB audio sigma-delta modulator in 90-nm CMOS

Abstract: A single-loop third-order switched-capacitor /spl Sigma/-/spl Delta/ modulator in 90-nm standard digital CMOS technology is presented. The design is intended to minimize the power consumption in a low-voltage environment. A load-compensated OTA with rail-to-rail output swing and gain enhancement is chosen in this design, which provides higher power efficiency than the two-stage OTA. To lower the power consumption further, class-AB operation is also adapted in the OTA design. Due to the relatively low threshold voltage of the advanced technology, no clock bootstrapping circuits are needed to drive the switches and the power consumption of the digital circuits is reduced. All the capacitors are implemented using multilayer metal-wall structure, which can provide high-density capacitance. The modulator achieves 88-dB dynamic range in 20-kHz signal bandwidth with an oversampling ratio of 100. The power consumption is 140 /spl mu/W under 1-V supply voltage and the chip core size is 0.18 mm/sup 2/.

Unified analysis of switched-capacitor resonant converters

Abstract: A family of switched-capacitor resonant circuits using only two transistors is presented. The circuit operates under zero-current switching and, therefore, the switching loss is zero. It also offers a wide choice of voltage conversions including fractional as well as multiple and inverted voltage conversion ratios.

Positive output multiple-lift push-pull switched-capacitor Luo-converters

Abstract: Micro-power-consumption technique requires high-power-density dc/dc converters and power supply source. Voltage lift technique is a popular method to apply in electronic circuit design. Since a switched capacitor can be integrated into a power IC chip, its size is small. Combining switched-capacitor and voltage lift technique can construct dc/dc converters with small size, high power density, high-voltage transfer gain, high power efficiency, and low electromagnetic interference. This paper introduces a new series of dc/dc converters-positive output multiple-lift push-pull switched-capacitor dc/dc Luo-converters.

Buck or boost tracking power converter

Abstract: A cascade of buck and boost converter is presented here. The control operates in a manner that the converter is either in buck or boost (BOB) mode on a cycle by cycle basis. It transitions between the modes seamlessly to provide a tracking power conversion function for modulating the power supply of a variable envelope radio frequency (RF) power amplifier. The control algorithm and its implementation using switched capacitor circuits is described. Simulation and measured experimental results including converter efficiency, tracking accuracy, and spectrum at the output of the RF power amplifier are provided. This control technique allows seamless transition between the buck and boost modes while tracking RF envelopes with bandwidth greater than 100 kHz, and maintaining extreme accuracy and extremely low ripple. The efficiency of this converter operating at 1.68 MHz is close to 90% over a wide range of conversion ratios. The area of the power converter is extremely small allowing this to be integrated into a cellular telephone. The controller was integrated as part of a larger power management IC as well as a discrete IC.

Direct RF sampling mixer with recursive filtering in charge domain

Abstract: We present a direct RF sampling technique in which an input RF signal is converted to a current waveform, gated and integrated on a sampling capacitor. A rotating capacitor shares this charge with the main sampling capacitor and transfers it to a subsequent discrete-time switched-capacitor filter stage. This action creates a first order IIR filter which serves as an anti-alias filter for subsequent stages. The transfer function of this stage can be changed by adjusting the clock signal controlling the rotating capacitor. This approach has been validated and incorporated in a commercial Bluetooth receiver IC realized in a digital 130 nm CMOS that meets or exceeds performance of other conventional Bluetooth radio architectures.

Switched-capacitor power supply system and method

Abstract: A plurality of thin-film capacitors are grouped in phases. A control circuit switches each phase between charging and discharging states devised to supply one or more loads with controlled power.

Resonant switched capacitor converter with high efficiency

Abstract: Conventional switched capacitor converters have an inherent drawback that their efficiency is much decreased as the output current is increased. This inherent drawback is due to a periodical forced charging and discharging operation in the internal switched capacitors accompanied by a large capacitor current, so that their efficiency can not be increased by decreasing its internal resistance. As a result, conventional switched capacitor converters have been limited to be used with a very small output current. This paper presents some novel switched capacitor converter topologies that use a resonant operation instead of the forced charging and discharging operation. Their advantage over conventional switched capacitor converters is a high efficiency even in a high output current region. The operation analysis and steady-state characteristics are described in detail for a half-buck type switched capacitor converter, and they are confirmed by experiments.

Differential capacitance measurement

Abstract: A circuit and method are given, which realizes a stable yet sensitive differential capacitance measuring device with good RF-suppression and with very acceptable noise features for use in capacitive sensor evaluation systems. By evaluating the difference of capacitor values only—with the help of a switched capacitor front-end—large spreads of transducer capacitor values are tolerable. Furthermore a mode of operation can be set up, where no essential galvanic connection between sensor input and the active read-out input at any given time is existing. The solution found exhibits a highly symmetrical construction. Using the intrinsic advantages of that solution the circuit of the invention is manufactured as an integrated circuit with standard CMOS technology at low cost.

Optimized reference voltage generation using switched capacitor scaling for data converters

Abstract: An algorithmic or cyclic data converter uses an RSD stage having a switched capacitor network for efficiently scaling at least one externally supplied reference voltage. A reference voltage is scaled by using capacitor ratios that also function to provide an output voltage used as a residue output of the RSD A/D converter. The residue is used to generate a bit value corresponding to the magnitude of the residue. Two RSD stages cycle back and forth generating a logic value each half clock cycle until the desired bit resolution is achieved. In one form, the RSD stage scales the externally supplied reference voltage only by factors of less than one. In another form, the RSD stage scales the reference voltage by any scaling factor. A reference voltage scaling circuit separate from the RSD stage is avoided.

A passive soft-switching snubber for PWM inverters

Abstract: This paper presents a regenerative passive snubber circuit for pulse-width modulation (PWM) inverters to achieve soft-switching purposes without significant cost and reliability penalties. This passive soft-switching snubber (PSSS) employs a diode/capacitor snubber circuit for each switching device in an inverter to provide low dv/dt and low switching losses to the device. The PSSS further uses a transformer-based energy regenerative circuit to recover the energy captured in the snubber capacitors. All components in the PSSS circuit are passive, thus leading to reliable and low-cost advantages over those soft-switching schemes relying on additional active switches. The snubber has been incorporated into a 150 kVA PWM inverter. Simulation and experimental results are given to demonstrate the validity and features of the snubber circuit.

A fourth-order single-bit switched-capacitor /spl Sigma/-/spl Delta/ modulator for distributed sensor applications

Abstract: In this paper, we present a switched-capacitor sigma-delta (/spl Sigma/-/spl Delta/) modulator for high resolution applications. In particular, this /spl Sigma/-/spl Delta/ modulator is well suited for distributed sensor networks. The circuit, implemented in a double-poly, double-metal 0.6 /spl mu/m CMOS technology, is based on a fourth-order single-loop architecture with a sampling frequency of 256 kHz. The chip consumes 50 mW from a single 5-V supply and achieves a signal-to-noise ratio of 104.9 dB over a bandwidth of 400 Hz, corresponding to a resolution of 17.1 bits.

A low-power switched-capacitor variable gain amplifier

Abstract: A novel power reduction technique is proposed for a switched-capacitor amplifier (SCA) with two-stage operational amplifier. This technique improves both the bandwidth and the slew rate of the SCA with only two additional switches, and therefore, the power consumption of the SCA is reduced. This power reduction technique is applied to a variable gain amplifier (VGA) which is implemented in an analog front-end of camera modules for cellular phones. This reduces 30% of the VGA power consumption compared to the conventional one. Fabricated in 0.25-/spl mu/m CMOS process with 3.3-V transistors and MIM capacitors, the VGA occupies 0.49/spl times/0.49 mm/sup 2/ and dissipates 18.7 mW at 18 MHz with a supply voltage of 3.1 V.

Semiconductor circuit device and data processing system

Abstract: Occurrence of power supply noise arising in connection with a step-down action at the time of turning on power supply is to be restrained. A step-down unit is provided with a switched capacitor type step-down circuit and a series regulator type step-down circuit, and stepped-down voltage output terminals of the step-down circuits are connected in common. The common connection of the stepped-down voltage output terminals of both step-down circuits makes possible parallel driving of both, selective driving of either or consecutive driving of the two. In the consecutive driving, even if the switched capacitor type step-down circuit is driven after driving the series regulator type step-down circuit first to supply a stepped-down voltage to loads, the switched capacitor type step-down circuit will need only to be compensated for a discharge due to the loads, and a peak of a charge current for capacitors can be kept low. When operation of the switched capacitor type step-down circuit is started, no large rush current arises, and occurrence of noise is restrained.

Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applications

Abstract: The authors present a new fully differential operational transconductance amplifier (OTA) for low-voltage and fast-settling switched-capacitor circuits in pure digital CMOS technology. The proposed two-stage OTA is a hybrid class A/AB that combines a folded cascode as the first stage with active current mirrors as the second stage. Owing to the class AB operation in the second stage, slew limiting occurs only in the first stage, resulting in low power dissipation for switched-capacitor circuits. It employs a novel hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensations, for fast settling. A design procedure for the minimum settling time of the proposed OTA is described. To demonstrate the efficiency of the proposed OTA and its compensation method three design examples are also provided.

A switched capacitor circuit compensation apparatus and method

Abstract: A compensated switched capacitor circuit comprises a switched capacitor circuit and a compensation circuit. The compensation circuit generates a reference current that varies under closed loop control to maintain a targeted slew rate for charging a reference capacitor that is determined by the input clock frequency. The switched capacitor circuit’s output amplifier is configured such that its output current varies in proportion to the reference current. Thus, by configuring the reference capacitor to track the effective capacitance of the switched capacitor circuit, the settling time of the switched capacitor circuit may be made relatively insensitive to the value of and changes in the effective capacitance over a range of clock frequencies. The compensation circuit may include a clock reconditioning circuit that the switched capacitor circuit is clocked at a desired duty cycle.

Design and analysis of power-CMOS-gate-based switched-capacitor boost DC-AC inverter

Abstract: A multistage power CMOS-transmission-gate-based (CMOS-TG) quasi-switched-capacitor (QSC) boost DC-AC inverter is proposed and integrated with a boost DC-DC converter for a step-up application with AC or DC load. In this paper, using CMOS-TG as a bidirectional switch, the various topologies can be integrated in the same configuration for achieving two functions: boosting and alternating; boosting for getting a sinusoidal output in which the peak is the result of a many times step-up of the input; alternating to realize the positive/negative half sinusoidal of the output. The inverter does not require any inductive elements as inductor and transformer, so integrated circuit (IC) fabrication will be promising for realization. By using the state-space averaging technique, the large-signal state-space model of the inverter is proposed, and then both the static analysis and dynamic small-signal analysis are derived to form a unified formulation for inverter/converter. Based on this formulation, there are presented for theoretical analysis/control design, including steady-state power, conversion efficiency, voltage conversion ratio, output ripple percentage, capacitance selection, closed-loop control and stability, and total harmonic distortion (THD), etc. Finally, a six-stage QSC boost DC-AC inverter is simulated by PSPICE, and the simulations are discussed for some cases, including: 1) steady-state AC output, ripple percentage, and power efficiency; 2) transient response of the regulated inverter for load variation; 3) a practical capacitive load: electromagnetic luminescent (EL) lamp, and 4) efficiency, ripple percentage, and THD for different loads. The results are illustrated to show the efficacy of the proposed inverter.

A 1-V low phase noise multi-band CMOS voltage controlled oscillator with switched inductors and capacitors

Abstract: A low voltage multi-band all PMOS VCO was fabricated in a 0.18-/spl mu/m CMOS process. By using a combination of inductor and capacitor switching, four band (2.4, 2.5, 4.7 and 5 GHz) operation was realized in a single VCO. The VCO with 1-V power supply has phase noises at 1-MHz offset of -126 dBc/Hz at 4.7 GHz and -134 dBc/Hz at 2.4 GHz, respectively. It has the lowest phase noise among the CMOS VCOs presented to date in all the bands. The VCO consumes 4.6 mW for 2.4 and 2.5 GHz, and 6 mW for 4.7 and 5 GHz operations, respectively.

Highly accurate switched capacitor DAC

Abstract: In one set of embodiments the invention comprises a highly accurate, low-power, compact size DAC utilizing charge redistribution techniques. Two complementary conversions may be performed and added together to form a final DAC output voltage by performing charge redistribution a first time, and again a second time in a complementary fashion, followed by a summing of the two charge distributions, in effect canceling the odd order capacitor mismatch errors. By canceling all odd order mismatch errors the accuracy of the DAC may become a function of the square of the mismatch of the two capacitors, resulting in greatly increased accuracy. When performing the complementary conversions for multiple bits, the sequence in which each of the two capacitors is charged may be determined to minimize the even-order errors, especially second-order errors. The DEM technique may be applied, in conjunction with the complementary conversions, with less oversampling than required by current DEM implementations, resulting in even-order errors being substantially reduced in addition to all odd-order errors being eliminated.

Single loop feed-forward modulator with summing flash quantizer and multi-bit feedback

Abstract: A sigma-delta modulator includes a summing junction that receives an input signal A plurality of integrators are arranged in series, the integrators output an integrated signal value to a multi-input quantizer The multi-input quantizer has a plurality of comparators each with switched capacitor inputs The multi-input quantizer outputs a quantized signal to a multi-bit feedback DAC that drives the summing junction

Current-fed multiple-output power conversion

Abstract: This paper focuses on low cost and low component count, multiple-output power conversion. The work is particularly applicable to both isolated and nonisolated conversion to multiple independently regulated low voltage outputs. The topology employed is a switch-mode current source feeding interleaved switched capacitor outputs. Several advances are presented. The output switches for the topology are implemented with two types of silicon for unidirectional current how. Firstly, with newly available power trench JFETs and then with proposed new "body-diode-less" N-channel MOSFETs. These have their internal body (base) regions separated from their source regions. A novel control scheme involving closed-loop control of the switching frequency to maintain the optimal source current is presented.

Switched capacitor filter and feedback system

Abstract: A switched capacitor filter comprises three switched capacitor circuits. Each switched capacitor circuit has a capacitance. A first state that the capacitance is connected to an input end of a current signal, a second state that the capacitance is connected to an output end of a voltage signal, and a third state that the capacitance is connected to a side of a filter capacitance, are cycled. These three switched capacitor circuits are operated under an interleave control so that the first to third states do not each overlap between the three switched capacitor circuits.

Capacitor switching transients: analysis and proposed technique for identifying capacitor size and location

Abstract: This paper deals with the analysis of transients initiated by the switching of shunt capacitors in power networks. These transients will propagate through the network along the transmission elements and will, accordingly, be felt at other locations far from the capacitors, such as load terminals. This can lead to adverse effects on the supply quality at those load buses. Based on a typical radial system, the distributed-parameter analysis will give analytical expressions for the expected transient voltages at the load terminals in terms of both the size and location of the switched capacitor. In its second part, this paper presents simple closed-form expressions for the accurate identification of the shunt capacitor's size and location, in terms of easily measurable parameters of the voltage signal at the load terminals.

Adiabatic Charging Reversible Logic Using a Switched Capacitor Regenerator

Abstract: This report describes a concrete method for realizing adiabatic charging reversible logic. First, we investigate the stabilization properties of a charge recycle regenerator using a switched capacitor circuit by SPICE simulation and an analytical method. In the N-step case, we proved that a step waveform is spontaneously generated. Next, for combinational logic, we propose an adiabatic charging binary decision diagram logic gate (AC-BDD) that uses this regenerator. The AC-BDD uses pass transistor logic based on a BDD, which is suitable for adiabatic logic. 8-bit AC-BDD multipliers were fabricated, and it is clarified that power consumption is reduced to 15% that of the same-rule-designed CMOS at 1 V and 1 MHz. Finally, we propose clocked energy reversible logic (CERL) that maintains the CMOS architecture for CMOS compatibility. CERL can reduce the clocked energy, which is used for charging the clock load capacitance, to 10% that of CMOS by using a power clock from the charge recycle regenerator.

Switched-current power converter

Abstract: In the switched-current power converter, a plurality of constant current sources provide equal currents to a plurality of switch pairs that may direct the several currents either to return or to the output capacitor and the load. The dynamic response to changes in load current can be nearly instantaneous, just as fast as the switches can switch. As an extreme example, if all terminal switches are switched from return to the output and then back to return, the switched-current power converter can go from zero load to full load and back to zero load nearly instantly, with no di/dt in the power distribution bus or the power source circuitry. Another embodiment of the invention incorporates switched-charge circuitry, so that the output voltage can step nearly instantly and precisely.

Digital-to-analogue converter circuits

Abstract: This invention is generally concerned with digital-to-analogue converters and more particularly relates to techniques for reducing signal dependent loading of reference voltage sources used by these converters. A differential switched capacitor digital-to-analogue (DAC) circuit ( 500 ) comprises first and second differential signal circuit portions ( 500 a,b ) for providing respective positive and negative signal outputs with respect to a reference level, and has first and second reference voltage inputs ( 112,114 ) for receiving respective positive and negative references. Each of said first and second circuit portions comprises an amplifier ( 102 a,b ) with a feedback capacitor ( 104 a,b ), a second capacitor ( 106 a,b ), and a switch ( 108 a,b, 110 a,b ) to switchably couple said second capacitor to a selected one of said reference voltage inputs to charge the second capacitor and to said feedback capacitor to share charge with the feedback capacitor. The switch of said first circuit portion is further configured to connect said second capacitor ( 106 a ) of said first circuit portion to share charge with said feedback capacitor ( 104 b ) of said second circuit portion; and the switch of said second circuit portion is further configured to connect said second capacitor ( 106 b ) of said second circuit portion to share charge with said feedback capacitor ( 104 a ) of said first circuit portion. This enables the second capacitors to in effect be alternately pre-charged to positive and negative signal-dependent nodes so that, on average, signal dependent loading of the references is approximately constant.

Switched-capacitor high-pass mirrored integrator

Abstract: In a high-pass (mirrored) integrator structure that employs chopper modulation, the input and output of the mirrored integrator are connected to the input and output ports of the operational amplifier, bypassing the chopper stabilization modulators. The mirrored integrator can be used in sigma-delta analog-to-digital converters.

A low power wide band CMOS VCO for multi-standard radios

Abstract: The work presents a single monolithic wide band VCO for multi-standard radios Analysis on a differential switched capacitor circuit is performed Its impact on phase noise and power dissipation is especially addressed The analysis is demonstrated and verified in a fully integrated CMOS VCO that consumes 27 mA from a 18 V supply and operates with a wide frequency band from 35-53 GHz The measured phase noise is less than -110 dBc/Hz at 1 MHz offset within the entire tuning range