Showing papers by "Samsung published in 2005"

On the practical genetic algorithms

Abstract: This paper offers practical design-guidelines for developing efficient genetic algorithms (GAs) to successfully solve real-world problems. As an important design component, a practical population-sizing model is presented and verified.

Secondary battery module

Abstract: A secondary battery module including a plurality of unit batteries that each include a cap plate and a case connected to either one of a positive electrode and a negative electrode of an electrode assembly and an electrode terminal connected to the other of the positive electrode and negative electrode, wherein the electrode terminal protrudes outside of a unit battery by passing through the cap plate covering the case, and a connector having a first end and a second end, wherein the first end fits on the electrode terminal of one of the unit batteries and is screw-engaged to the electrode terminal by a nut and the second end is connected to the case of another adjacent unit battery.

An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system

Abstract: An ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18-/spl mu/m CMOS technology for a 3.1-5-GHz UWB system. Measurements show a -3-dB gain bandwidth of 2-4.6GHz, a minimum NF of 2.3 dB, a power gain of 9.8 dB, better than -9 dB of input matching, and an input IP3 of -7dBm, while consuming only 12.6 mW of power.

Backlight assembly and liquid crystal display apparatus having the same

Abstract: A backlight assembly includes a lamp assembly generating light, a light guide plate changing a path of light incident from the lamp assembly, a receiving container having a bottom part and a side part vertically extending from the bottom part and forming a receiving space, and an adhesive member fixing the light guide plate to the receiving container The light guide plate includes a prism pattern on a surface, and the adhesive member is attached to a light-adjusting portion opposite to the lamp assembly Therefore, the light guide plate may be affixed to the receiving container without additional structure and the appearance of the backlight assembly may be improved by preventing modification of the prism pattern

Enhanced light extraction from GaN-based light-emitting diodes with holographically generated two-dimensional photonic crystal patterns

Abstract: We observed a significant enhancement in light output from GaN-based light-emitting diodes (LEDs) in which two-dimensional photonic crystal (PC) patterns were integrated. Two-dimensional square-lattice air-hole array patterns with a period that varied from 300 to 700 nm were generated by laser holography. Unlike the commonly utilized electron-beam lithographic technique, the holographic method can make patterns over a large area with high throughput. The resultant PC-LED devices with a pattern period of ∼500nm had more than double the output power, as measured from the top of the device. The experimental observations are qualitatively consistent with the results of three-dimensional finite-difference-time-domain simulation.

Locally linear discriminant analysis for multimodally distributed classes for face recognition with a single model image

Abstract: We present a novel method of nonlinear discriminant analysis involving a set of locally linear transformations called "Locally Linear Discriminant Analysis" (LLDA). The underlying idea is that global nonlinear data structures are locally linear and local structures can be linearly aligned. Input vectors are projected into each local feature space by linear transformations found to yield locally linearly transformed classes that maximize the between-class covariance while minimizing the within-class covariance. In face recognition, linear discriminant analysis (LIDA) has been widely adopted owing to its efficiency, but it does not capture nonlinear manifolds of faces which exhibit pose variations. Conventional nonlinear classification methods based on kernels such as generalized discriminant analysis (GDA) and support vector machine (SVM) have been developed to overcome the shortcomings of the linear method, but they have the drawback of high computational cost of classification and overfitting. Our method is for multiclass nonlinear discrimination and it is computationally highly efficient as compared to GDA. The method does not suffer from overfitting by virtue of the linear base structure of the solution. A novel gradient-based learning algorithm is proposed for finding the optimal set of local linear bases. The optimization does not exhibit a local-maxima problem. The transformation functions facilitate robust face recognition in a low-dimensional subspace, under pose variations, using a single model image. The classification results are given for both synthetic and real face data.

Multi-layer cross-point binary oxide resistive memory (OxRRAM) for post-NAND storage application

Abstract: Feasibility of the multi-layer cross-point structured binary oxide resistive memory (OxRRAM) has been tested for next generation non-volatile random access high density data storage application Novel plug contact type bottom electrode (plug-BE) could reduce active memory cell diameter down to 50nm with smaller operation current and improved switching distributions With 2 additional masks, one layer of plug-BE included cross-point memory array could be added on top of another one No signal of inter-layer interference has been observed Also, prototype binary oxide based diodes have been fabricated for the purpose of suppressing intra-layer interference of cross-point memory array

Quasi-cyclic LDPC codes for fast encoding

Abstract: In this correspondence we present a special class of quasi-cyclic low-density parity-check (QC-LDPC) codes, called block-type LDPC (B-LDPC) codes, which have an efficient encoding algorithm due to the simple structure of their parity-check matrices. Since the parity-check matrix of a QC-LDPC code consists of circulant permutation matrices or the zero matrix, the required memory for storing it can be significantly reduced, as compared with randomly constructed LDPC codes. We show that the girth of a QC-LDPC code is upper-bounded by a certain number which is determined by the positions of circulant permutation matrices. The B-LDPC codes are constructed as irregular QC-LDPC codes with parity-check matrices of an almost lower triangular form so that they have an efficient encoding algorithm, good noise threshold, and low error floor. Their encoding complexity is linearly scaled regardless of the size of circulant permutation matrices.

High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability

Abstract: For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process With 10nm diameter nanowire, saturation currents through twin nanowires of 264 mA/mum, 111 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively No roll-off of threshold voltages, ~70 mV/dec of substhreshold swing (SS), and ~20 mV/V of drain induced barrier lowering(DIBL) down to 30 nm gate length are observed for both n-ch and p-ch TSNWFETs

Reliability investigations for manufacturable high density PRAM

Abstract: In this paper, PRAM (phase-change memory), exploiting new memory materials called chalcogenides, is introduced. The reliability issues for high-density commercial memory products such as disturbance immunity, endurance, and data retention are addressed and evaluated by using a 64 Mb PRAM with 0.12 /spl mu/m technology. Moreover, observed degradation modes and underlying physical mechanisms are investigated.

Strongly Enhanced Phosphor Efficiency in GaInN White Light-Emitting Diodes Using Remote Phosphor Configuration and Diffuse Reflector Cup

Abstract: Enhancement of phosphor efficiency is reported for GaInN-based white light-emitting diodes (LEDs) employing a large separation between the primary LED emitter and the wavelength converter, and a diffuse reflector cup. Ray-tracing simulations show that extraction efficiency of wavelength-converted light is enhanced by 75%. The experimental improvement in phosphor efficiency of blue-pumped yellow phosphor is 15.4% compared with conventional phosphor-based white LEDs. The improvement is attributed to reduced re-absorption of wavelength-converted light by the LED chip.

Apparatus and method for measuring quantity of physical exercise using acceleration sensor

Abstract: Disclosed are a method for measuring quantity of exercise and an apparatus comprising an acceleration sensor for generating acceleration information by measuring the quantity of exercise according to user movement, sensor control unit for supplying power to the acceleration sensor and sampling the acceleration information generated from the acceleration sensor, a dynamic energy measurement unit for converting the sampled acceleration information into dynamic energy, comparing a local maximum value with a predetermined threshold value if an ascending gradient of the dynamic energy has the local maximum value exceeding a pre-determined value and determining a user step if the local maximum value exceeds the predetermined threshold value, a calorie consumption measurement unit for calculating calorie consumption by analyzing an energy level of dynamic energy determined as a user step, a memory for storing information, and a display section for displaying information related to the number of steps and calorie consumption.

On-chip antennas in silicon ICs and their application

Abstract: The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction between transmitted and received signals, and nearby circuits appear to be manageable This technology can potentially be applied for implementation of a true single-chip radio for general purpose communication, on-chip and inter-chip data communication systems, RFID tags, RF sensors/radars, and others

Highly reliable 50nm contact cell technology for 256Mb PRAM

Abstract: Novel small contact fabrication technologies were proposed to realize reliable high density 256Mb PRAM(phase change memory) product. Introducing the 2-step CMP (chemical mechanical polishing) process and the ring-shaped contact structure, the contact area distribution was greatly improved even at the smallest contact diameter of 50nm node. The validity of this approach was directly confirmed by the evaluation of the functionality for the fabricated 256Mbit PRAM based on 0.10/spl mu/m CMOS technology.

Analytical investigation of spin-transfer dynamics using a perpendicular-to-plane polarizer

Abstract: We studied current-induced magnetic switching and excitations in structures comprising a free layer with in-plane magnetization traversed by a current with perpendicular-to-plane spin polarization. We derived analytical solutions from the Landau–Lifshitz–Gilbert equation including the spin-torque term, and compared them to numerical simulations within the single domain assumption. Taking into account the criterion of thermal stability, the magnetization switching in nanostructures of typical size below 100nm comprising a perpendicular polarizer is found to require larger current density but to be much faster than with a longitudinal polarizer. Furthermore, a steady precession of magnetization can be generated in this geometry; those frequencies can be tuned from about 1 to 20GHz by only changing the current without applying any external field. This opens a promising application as microwave sources.

Highly scalable on-axis confined cell structure for high density PRAM beyond 256Mb

Abstract: We firstly fabricated on-axis confined structure and evaluated based on 64Mb PRAM with 0.12/spl mu/m-CMOS technologies. Ge/sub 2/Sb/sub 2/Te /sub 5/ was confined within small pore, which resulted in low writing current of 0.4mA. The pore is on-axis with upper and lower contacts, which leads to good scalability of PRAM above 256Mb. The confined structure was relatively insensitive to small cell edge damage effect. The on-axis confined structure is a promising candidate for high density PRAM due to low writing current, good scalability, and insensitiveness to edge damage.

Liquid crystal display device and manufacturing method thereof

Abstract: A liquid crystal display device comprises at least two insulating layers formed on a first conductive layer, a second conductive layer formed between the at least two insulating layers, a first contact hole penetrating an upper insulating layer of the at least two insulating layers on the second conductive layer, a second contact hole penetrating the at least two insulating layers and exposing a portion of the first conductive layer, and a contact part comprising a bridge electrode formed of a third conductive layer for connecting the first and second conductive layers through the first and second contact holes. The second contact hole comprises an internal hole penetrating the at least two insulating layers and an external hole surrounding the internal hole forming in the upper insulating layers.

Light emitting diode and lens for the same

Abstract: A light emitting diode includes a lens, a chip base attached to a bottom of the lens, and an LED chip attached in the chip base to be concentric with the lens. The lens includes a bottom, an outer sidewall extending from the bottom, a first outer top surface extending from the outer sidewall, a second outer top surface extending from the first outer top surface and having a substantially conical groove-like shape, an inner sidewall forming a side of a central cavity formed by hollowing a central portion of the bottom, and an inner top surface extending from the inner sidewall and forming a ceiling of the central cavity. The substantially conical groove-like shaped second outer top surface has an angular point formed toward the central cavity, and the inner top surface is convexly formed toward the bottom.

Design of low-pass filters using defected ground structure

Abstract: A method to design low-pass filters (LPF) having a defected ground structure (DGS) and broadened transmission-line elements is proposed. The previously presented technique for obtaining a three-stage LPF using DGS by Lim et al. is generalized to propose a method that can be applied in design N-pole LPFs for N/spl les/5. As an example, a five-pole LPF having a DGS is designed and measured. Accurate curve-fitting results and the successive design process to determine the required size of the DGS corresponding to the LPF prototype elements are described. The proposed LPF having a DGS, called a DGS-LPF, includes transmission-line elements with very low impedance instead of open stubs in realizing the required shunt capacitance. Therefore, open stubs, teeor cross-junction elements, and high-impedance line sections are not required for the proposed LPF, while they all have been essential in conventional LPFs. Due to the widely broadened transmission-line elements, the size of the DGS-LPF is compact.

Light emitting display and driving method thereof

Abstract: A light emitting display including data lines for applying data voltages corresponding to video signals, scan lines for transmitting select signals, and pixel circuits. Each pixel circuit includes a light emitting element for emitting light, and a transistor including first to third electrodes, for controlling a current output to the third electrode according to a voltage between the first and second electrodes. Each pixel circuit also includes a first switch for diode-connecting the transistor, a capacitor having a first electrode coupled to the first electrode of the transistor, a second switch for applying a corresponding said data voltage to the second electrode of the capacitor in response to a corresponding said select signal from a corresponding said scan line, and a third switch for substantially electrically decoupling the second electrode of the capacitor from a power supply voltage source.

Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times

Abstract: This work presents an intraprocess dynamic voltage and frequency scaling (DVFS) technique targeted toward nonreal-time applications running on an embedded system platform. The key idea is to make use of runtime information about the external memory access statistics in order to perform CPU voltage and frequency scaling with the goal of minimizing the energy consumption while translucently controlling the performance penalty. The proposed DVFS technique relies on dynamically constructed regression models that allow the CPU to calculate the expected workload and slack time for the next time slot and, thus, adjust its voltage and frequency in order to save energy, while meeting soft timing constraints. This is, in turn, achieved by estimating and exploiting the ratio of the total off-chip access time to the total on-chip computation time. The proposed technique has been implemented on an XScale-based embedded system platform and actual energy savings have been calculated by current measurements in hardware. For memory-bound programs, a CPU energy saving of more than 70% with a performance degradation of 12% was achieved. For CPU-bound programs, 15% /spl sim/ 60% CPU energy saving was achieved at the cost of 5%-20% performance penalty.

Application of time-frequency domain reflectometry for detection and localization of a fault on a coaxial cable

Abstract: In this paper, we introduce a new high-resolution reflectometry technique that operates simultaneously in both the time and frequency domains. The approach rests upon time-frequency signal analysis and utilizes a chirp signal multiplied by a Gaussian time envelope. The Gaussian envelope provides time localization, while the chirp allows one to excite the system under test with a swept sinewave covering a frequency band of interest. This latter capability is of particular interest when testing communication cables and systems. Sensitivity in detecting the reflected signal is provided by a time-frequency cross-correlation function. The approach is verified by experimentally locating various types of faults, located at various distances, in RG 142 and RG 400 coaxial cables.

Chemical vapor deposition apparatus

Abstract: A chemical vapor deposition apparatus includes a source gas box, a process chamber, a vacuum pump, a discharge pipe pressure sensor, a dump line and a pressure sensor protecting valve. The source gas box produces source gas by bubbling an inactive gas through a source solution. A metal thin film is formed on a wafer in the chamber under predetermined temperature and pressure using the source gas. The vacuum pump discharges residual gas from the chamber through discharge piping extending from the chamber. The discharge pipe pressure sensor senses the pressure within the discharge piping. The dump line bypasses the process chamber. The pressure sensor protecting valve prevents source gas and the like from flowing to the discharge pipe pressure sensor when the source gas is discharged through the dump line during a dummy flow operation.

Technology for sub-50nm DRAM and NAND flash manufacturing

Abstract: This paper discusses whether memory technologies can continue advances beyond sub-50nm node especially for DRAM and NAND flash memories First, the barriers to shrink technology are addressed for DRAM and NAND flash memories, depending on their inherent operation principles Then, details of technology solutions are introduced and its manufacturability is examined Beyond 30nm node, It is expected that 3-dimensional transistor scheme is needed for both logic and memory array in addition to the development of new materials and structural technologies

A new SLM OFDM scheme with low complexity for PAPR reduction

Abstract: The authors introduce a new selected mapping (SLM) orthogonal frequency division multiplexing (OFDM) scheme with low computational complexity. The proposed SLM scheme transforms an input symbol sequence into a set of OFDM signals by multiplying the phase sequences to the signal after a certain intermediate stage of inverse fast Fourier transform (IFFT). Then, the OFDM signal with the lowest peak-to-average power ratio (PAPR) is selected for transmission. The new SLM OFDM scheme reduces the computational complexity, while it shows almost the same performance of PAPR reduction as that of the conventional SLM OFDM scheme.

Block-based noise estimation using adaptive Gaussian filtering

Abstract: This paper proposes a fast noise estimation algorithm using a Gaussian filter. It is based on block-based noise estimation, in which an input image is assumed to be contaminated by the additive white Gaussian noise and a filtering process is performed by an adaptive Gaussian filter. Coefficients of a Gaussian filter are selected as functions of the standard deviation of the Gaussian noise that is estimated from an input noisy image. For estimation of the amount of noise (i.e., standard deviation of the Gaussian noise), we split an image into a number of blocks and select smooth blocks that are classified by the standard deviation of intensity of a block, where the standard deviation is computed from the difference of the selected block images between the noisy input image and its filtered image. In the experiments, the performance of the proposed algorithm is compared with that of the three conventional (block-based and filtering-based) noise estimation methods. Experiments with several still images show the effectiveness of the proposed algorithm. The proposed noise estimation algorithm can be efficiently applied to noise reduction in commercial image - or video-based applications such as digital cameras and digital television (DTV) for its performance and simplicity.