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Showing papers in "Journal of Electronic Packaging in 2016"


Journal ArticleDOI
TL;DR: In this article, a review of the most commonly used measurement techniques for thermal conductivity and interfacial thermal conductance is presented, including the 3-omega method and transient plane source method.
Abstract: Thermal conductivity and interfacial thermal conductance play crucial roles in the design of engineering systems where temperature and thermal stress are of concerns. To date, a variety of measurement techniques are available for both bulk and thin film solid-state materials with a broad temperature range. For thermal characterization of bulk material, the steady-state absolute method, laser flash diffusivity method, and transient plane source method are most used. For thin film measurement, the 3{\omega} method and transient thermoreflectance technique including both frequency-domain and time-domain analysis are employed widely. This work reviews several most commonly used measurement techniques. In general, it is a very challenging task to determine thermal conductivity and interface contact resistance with less than 5% error. Selecting a specific measurement technique to characterize thermal properties need to be based on: 1) knowledge on the sample whose thermophysical properties is to be determined, including the sample geometry and size, and preparation method; 2) understanding of fundamentals and procedures of the testing technique and equipment, for example, some techniques are limited to samples with specific geometrics and some are limited to specific range of thermophysical properties; 3) understanding of the potential error sources which might affect the final results, for example, the convection and radiation heat losses.

306 citations


Journal ArticleDOI
TL;DR: In this article, the authors summarized the recent progress in the packaging of QD-LEDs and discussed the wide applications of QDs in lighting and display, followed by the challenges and corresponding progresses for the QDLEDs' packaging.
Abstract: Recent years, semiconductor quantum dots (QDs) have attracted tremendous attentions for their unique characteristics for solid-state lighting (SSL) and thin-film display applications. The pure and tunable spectra of QDs make it possible to simultaneously achieve excellent color-rendering properties and high luminous efficiency (LE) when combining colloidal QDs with light-emitting diodes (LEDs). Due to its solution-based synthetic route, QDs are impractical for fabrication of LED. QDs have to be incorporated into polymer matrix, and the mixture is dispensed into the LED mold or placed onto the LED to fabricate the QD–LEDs, which is known as the packaging process. In this process, the compatibility of QDs’ surface ligands with the polymer matrix should be ensured, otherwise the poor compatibility can lead to agglomeration or surface damage of QDs. Besides, combination of QDs–polymer with LED chip is a key step that converts part of blue light into other wavelengths (WLs) of light, so as to generate white light in the end. Since QD-LEDs consist of three or more kinds of QDs, the spectra distribution should be optimized to achieve a high color-rendering ability. This requires both theoretical spectra optimization and experimental validation. In addition, to prolong the reliability and lifetime of QD-LEDs, QDs have to be protected from oxygen and moisture penetration. And the heat generation inside the package should be well controlled because high temperature results in QDs’ thermal quenching, consequently deteriorates QD-LEDs’ performance greatly. Overall, QD-LEDs’ packaging and applications present the abovementioned technical challenges. A profound and comprehensive understanding of these problems enables the advancements of QD-LEDs’ packaging processes and designs. In this review, we summarized the recent progress in the packaging of QD-LEDs. The wide applications of QD-LEDs in lighting and display were overviewed, followed by the challenges and the corresponding progresses for the QD-LEDs’ packaging. This is a domain in which significant progress has been achieved in the last decade, and reporting on these advances will facilitate state-of-the-art QD-LEDs’ packaging and application technologies. [DOI: 10.1115/1.4033143]

146 citations


Journal ArticleDOI
TL;DR: In this article, a review of the current technology development of sintered Ag as a bonding material from the perspective of patents filed by various stakeholders since late 1980s is presented.
Abstract: Sintered silver joint is a porous silver that bonds a semiconductor die to the substrate as part of the packaging process. Sintered Ag is one of the few possible bonding methods to fulfill the operating conditions of wide band-gap (WBG) power device technologies. We review the current technology development of sintered Ag as a bonding material from the perspective of patents filed by various stakeholders since late 1980s. This review addresses the formulation of sintered pastes (i.e., nano-Ag, hybrid Ag, and micron Ag fillers), innovations in the process and equipment to form this Ag joint. This review will provide the insights and confidence to engineers, scientists from universities and industry as well as investors who are developing and commercializing the sintered Ag as a bonding material for microelectronic packaging. [DOI: 10.1115/1.4033069]

121 citations




Journal ArticleDOI
TL;DR: In this paper, the authors proposed and simulated GaN-based HEMT technologies that can remove power densities exceeding 30 kW/cm2 at relatively low mass flow rate and pressure drop.
Abstract: Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) dissipate high power densities which generate hotspots and cause thermomechanical problems. Here, we propose and simulate GaN-based HEMT technologies that can remove power densities exceeding 30 kW/cm2 at relatively low mass flow rate and pressure drop. Thermal performance of the microcooler module is investigated by modeling both single- and two-phase flow conditions. A reduced-order modeling approach, based on an extensive literature review, is used to predict the appropriate range of heat transfer coefficients associated with the flow regimes for the flow conditions. Finite element simulations are performed to investigate the temperature distribution from GaN to parallel microchannels of the microcooler. Single- and two-phase conjugate computational fluid dynamics (CFD) simulations provide a lower bound of the total flow resistance in the microcooler as well as overall thermal resistance from GaN HEMT to working fluid. A parametric study is performed to optimize the thermal performance of the microcooler. The modeling results provide detailed flow conditions for the microcooler in order to investigate the required range of heat transfer coefficients for removal of heat fluxes up to 30 kW/cm2 and a junction temperature maintained below 250 °C. The detailed modeling results include local temperature and velocity fields in the microcooler module, which can help in identifying the approximate locations of the maximum velocity and recirculation regions that are susceptible to dryout conditions.

58 citations



Journal ArticleDOI
TL;DR: In this paper, the effect of wetting conditions of the solid surface has been investigated to investigate the boiling phenomena of thin liquid film adsorbed on a nanostructured solid surface.
Abstract: Molecular dynamics (MDs) simulations have been performed to investigate the boiling phenomena of thin liquid film adsorbed on a nanostructured solid surface with particular emphasis on the effect of wetting condition of the solid surface. The molecular system consists of liquid and vapor argon and solid platinum wall. The nanostructures which reside on top of the solid wall have shape of rectangular block. The solid–liquid interfacial wettability, in other words whether the solid surface is hydrophilic or hydrophobic, has been altered for different cases to examine its effect on boiling phenomena. The initial configuration of the simulation domain comprises a three-phase system (solid platinum, liquid argon, and vapor argon), which was equilibrated at 90 K. After equilibrium period, the wall temperature was suddenly increased from 90 K to 250 K which is far above the critical point of argon and this initiates rapid or explosive boiling. The spatial and temporal variation of temperature and density as well as the variation of system pressure with respect to time were closely monitored for each case. The heat flux normal to the solid surface was also calculated to illustrate the effectiveness of heat transfer for different cases of wetting conditions of solid surface. The results show that the wetting condition of surface has significant effect on explosive boiling of the thin liquid film. The surface with higher wettability (hydrophilic) provides more favorable conditions for boiling than the low-wetting surface (hydrophobic), and therefore, the liquid argon responds quickly and shifts from liquid to vapor phase faster in the case of hydrophilic surface. The heat transfer rate is also much higher in the case of hydrophilic surface.

32 citations



Journal ArticleDOI
TL;DR: In this article, an advanced complementary metal oxide silicon (CMOS) test chip with programmable power distribution has been designed, fabricated, stacked, and packaged in molded and bare die 3D packages.
Abstract: In this paper, we present the experimental characterization of three-dimensional (3D) packages using a dedicated stackable test chip. An advanced complementary metal oxide silicon (CMOS) test chip with programmable power distribution has been designed, fabricated, stacked, and packaged in molded and bare die 3D packages. The packages have been experimentally characterized in test sockets with and without cooling and soldered to the printed circuit board (PCB). Using uniform and localized hot spot power distribution, the thermal self-heating and thermal coupling resistance and the lateral spreading in the 3D packages have been studied. Furthermore, the measurements have been used to characterize the thermal properties of the die–die interface and to calibrate a thermal model for the calculation of equivalent properties of underfilled μbump arrays. This model has been applied to study the tradeoff between the standoff height reduction and the underfill thermal conductivity increase in order to reduce the interdie thermal resistance.

25 citations




Journal ArticleDOI
TL;DR: Several families of polymers have been used as sacrificial, templating polymers including polycarbonates, polynorbornenes (PNBs), and polyaldehydes as discussed by the authors.
Abstract: Polymers can be used as temporary place holders in the fabrication of embedded air gaps in a variety of electronic devices. Embedded air cavities can provide the lowest dielectric constant and loss for electrical insulation, mechanical compliance in devices where low-force deformations are desirable, and can temporarily protect movable parts during processing. Several families of polymers have been used as sacrificial, templating polymers including polycarbonates, polynorbornenes (PNBs), and polyaldehydes. The families can be distinguished by chemical structure and decomposition temperature. The decomposition temperature ranges from over 400 C to below room temperature in the case of low ceiling temperature polymers. Overcoat materials include silicon dioxide, polyimides, epoxy, and bis-benzocyclobutene (BCB). The methods of air-gap fabrication are discussed. Finally, the use of photoactive compounds in the patterning of the sacrificial polymers is reviewed. [DOI: 10.1115/1.4033000]


Journal ArticleDOI
TL;DR: In this article, a test facility is developed to experimentally characterize performance and analyze the behavior of ultrathin vapor chambers that must reject heat to the ambient via natural convection.
Abstract: Vapor chamber technologies offer an attractive approach for passive cooling in portable electronic devices. Due to the market trends in device power consumption and thickness, vapor chamber effectiveness must be compared with alternative heat spreading materials at ultrathin form factors and low heat dissipation rates. A test facility is developed to experimentally characterize performance and analyze the behavior of ultrathin vapor chambers that must reject heat to the ambient via natural convection. The evaporator-side and ambient temperatures are measured directly; the condenser-side surface temperature distribution, which has critical ergonomics implications, is measured using an infrared (IR) camera calibrated pixel-by-pixel over the field of view and operating temperature range. The high thermal resistance imposed by natural convection in the vapor chamber heat dissipation pathway requires accurate prediction of the parasitic heat losses from the test facility using a combined experimental and numerical calibration procedure. Solid metal heat spreaders of known thermal conductivity are first tested, and the temperature distribution is reproduced using a numerical model for conduction in the heat spreader and thermal insulation by iteratively adjusting the external boundary conditions. A regression expression for the heat loss is developed as a function of measured operating conditions using the numerical model. A sample vapor chamber is tested for heat inputs below 2.5 W. Performance metrics are developed to characterize heat spreader performance in terms of the effective thermal resistance and the condenser-side temperature uniformity. The study offers a rigorous approach for testing and analysis of new vapor chamber designs, with accurate characterization of their performance relative to other heat spreaders.

Journal ArticleDOI
TL;DR: In this article, a review of fundamental experimental studies on flow boiling in plain and surface enhanced microgaps is presented, and new results of subcooled flow boiling of water through a micropin-fin array heat sink with outlet pressure below atmospheric are presented.
Abstract: In the first part of this paper, a review of fundamental experimental studies on flow boiling in plain and surface enhanced microgaps is presented. In the second part, complimentary to the literature review, new results of subcooled flow boiling of water through a micropin-fin array heat sink with outlet pressure below atmospheric are presented. A 200 lm high microgap device design was tested, with a longitudinal pin pitch of 225 lm, a transverse pitch of 135 lm, and a diameter of 90 lm, respectively. Tested mass fluxes ranged from 1351 to 1784 kg=ms, and effective heat flux ranged from 198 to 444 W/cm based on the footprint surface area. The inlet temperature varied from 6 to 12 C, and outlet pressure ranged from 24 to 36 kPa. The two-phase heat transfer coefficient showed a decreasing trend with increasing heat flux. High-speed visualizations of flow patterns revealed a triangular wake after bubble nucleation. Flow oscillations were seen and discussed. [DOI: 10.1115/1.4034317]


Journal ArticleDOI
TL;DR: In this article, an analytical solution using Ritz method for the electronic assembly vibration problem has been presented in detail, where a special treatment for plate-mounted-on-standoffs boundary conditions scheme was required, and hence described.
Abstract: An analytical solution using Ritz method for the electronic assembly vibration problem has been presented in detail. In this solution, a special treatment for plate-mounted-on-standoffs boundary conditions scheme was required, and hence described. Also, a simple equation for estimating ball grid array (BGA) solder joint axial stiffness was developed. The results of the analytical solution were validated with modal analysis measurements and finite element (FE) models data in terms of natural frequencies and mode shapes. Then, the analytical solution was used to estimate the most critical solder joint deformations and stresses. Finally, the so developed solution provided an effective tool to examine the effect of several geometric and material configurations of electronic package structure on the fatigue performance of electronic products under mechanical vibration loadings.


Journal ArticleDOI
TL;DR: An overview of the thermal management landscape with focus on heat dissipation from three-dimensional (3D) chip stacks is provided in this article, where three topologies, namely, single-side, dual-side and finally, volumetric heat removal, are benchmarked with respect to a high-performance three-tier chip stack with an aggregate power dissipation of 672 W.
Abstract: An overview of the thermal management landscape with focus on heat dissipation from three-dimensional (3D) chip stacks is provided in this study. Evolutionary and revolutionary topologies, such as single-side, dual-side, and finally, volumetric heat removal, are benchmarked with respect to a high-performance three-tier chip stack with an aggregate power dissipation of 672 W. The thermal budget of 50 K can be maintained by three topologies, namely: (1) dual-side cooling, implemented by a thermally active interposer, (2) interlayer cooling with four-port fluid delivery and drainage at 100 kPa pressure drop, and (3) a hybrid approach combining interlayer with embedded back-side cooling. Of all the heat-removal concepts, interlayer cooling is the only approach that scales with the number of dies in the chip stack and hence enables extreme 3D integration. However, the required size of the microchannels competes with the requirement of low through-siliconvia (TSV) heights and pitches. A scaling study was performed to derive the TSV pitch that is compatible with cooling channels to dissipate 150 W/cm per tier. An active integrated circuit (IC) area of 4 cm was considered, which had to be implemented on the varying tier count in the stack. A cuboid form factor of 2 mm 4 mm 2.55 mm results from a die count of 50. The resulting microchannels of 2 mm length allow small hydraulic diameters and thus a very high TSV density of 1837 1/mm. The accumulated heat flux and the volumetric power dissipation are as high as 7.5 kW/cm and 29 kW/cm, respectively. [DOI: 10.1115/1.4032492]

Journal ArticleDOI
TL;DR: In this article, an extensive experimental study was conducted to investigate the base temperature response of multi-microchannel evaporators under transient heat loads, including cold startups and periodic step variations in heat flux using two different test sections and two coolants (R236fa and R245fa).
Abstract: Multi-microchannel evaporators with flow boiling, used for cooling high heat flux devices, usually experience transient heat loads in practical applications. These transient processes may cause failure of devices due to a thermal excursion or poor local cooling or dryout. However, experimental studies on such transient thermal behavior of multi-microchannel evaporators during flow boiling are few. Thus, an extensive experimental study was conducted to investigate the base temperature response of multi-microchannel evaporators under transient heat loads, including cold startups and periodic step variations in heat flux using two different test sections and two coolants (R236fa and R245fa) for a wide variety of flow conditions. The effects on the base temperature behavior of the test section, heat flux magnitude, mass flux, inlet subcooling, outlet saturation temperature, and fluid were investigated. The transient base temperature response, monitored by an infrared (IR) camera, was recorded simultaneously with the flow regime acquired by a high-speed video camera. For cold startups, it was found that reducing the inlet orifice width, heat flux magnitude, inlet subcooling, and outlet saturation temperature but increasing the mass flux decreased the maximum base temperature. Meanwhile, the time required to initiate boiling increased with the inlet orifice width, mass flux, inlet subcooling, and outlet saturation temperature but decreased with the heat flux magnitude. For periodic variations in heat flux, the resulting base temperature was found to oscillate and then damp out along the flow direction. Furthermore, the effects of mass flux and heat flux pulsation period were insignificant.

Journal ArticleDOI
TL;DR: In this article, a thermal testbed with embedded micropin-fin heat sinks that were designed and microfabricated in silicon was presented, and the results obtained from the two testbeds were compared and analyzed.
Abstract: This paper reports on novel thermal testbeds with embedded micropin-fin heat sinks that were designed and microfabricated in silicon. Two micropin-fin arrays were presented, each with a nominal pin height of 200 lm and pin diameters of 90 lm and 30 lm. Singlephase and two-phase thermal testing of the micropin-fin array heat sinks were performed using de-ionized (DI) water as the coolant. The tested mass flow rate was 0.001 kg/s, and heat flux ranged from 30 W/cm to 470 W/cm. The maximum heat transfer coefficient reached was 60 kW/m K. The results obtained from the two testbeds were compared and analyzed, showing that density of the micropin-fins has a significant impact on thermal performance. The convective thermal resistance in the single-phase region was calculated and fitted to an empirical model. The model was then used to explore the tradeoff between the electrical and thermal performance in heat sink design. [DOI: 10.1115/1.4032496]


Journal ArticleDOI
TL;DR: In this paper, the authors evaluate the true total cost of ownership (TCO) for water-cooled data centers by considering the combined capital and operational cost for both the IT systems and the data center facility.
Abstract: The generation-to-generation information technology (IT) performance and density demands continue to drive innovation in data center cooling technologies. For many applications, the ability to efficiently deliver cooling via traditional chilled air cooling approaches has become inadequate. Water cooling has been used in data centers for more than 50 years to improve heat dissipation, boost performance, and increase efficiency. While water cooling can undoubtedly have a higher initial capital cost, water cooling can be very cost effective when looking at the true life cycle cost of a water-cooled data center. This study aims at addressing how one should evaluate the true total cost of ownership (TCO) for water-cooled data centers by considering the combined capital and operational cost for both the IT systems and the data center facility. It compares several metrics, including return-on-investment for three cooling technologies: traditional air cooling, rack-level cooling using rear door heat exchangers, and direct water cooling (DWC) via cold plates. The results highlight several important variables, namely, IT power, data center location, site electric utility cost, and construction costs and how each of these influences the TCO of water cooling. The study further looks at implementing water cooling as part of a new data center construction project versus a retrofit or upgrade into an existing data center facility.




Journal ArticleDOI
TL;DR: In this paper, a lid-integral silicon cold-plate topology is proposed to bring liquid cooling closer to the heat source integrated circuit (IC) to eliminate one thermal interface material (TIM2), to establish and improve TIM1 during packaging, to use wafer-level processes, and to ease integration in first level packaging.
Abstract: We demonstrate the lid-integral silicon cold-plate topology as a way to bring liquid cooling closer to the heat source integrated circuit (IC). It allows us to eliminate one thermal interface material (TIM2), to establish and improve TIM1 during packaging, to use wafer-level processes, and to ease integration in first-level packaging. We describe the integration and analyze the reliability aspects of this package using modeling and test vehicles. To compare the impact of geometry, materials, and mechanical coupling on warpage, strains, and stresses, we simulate finite element models of five different topologies on an organic land-grid array (LGA) carrier. We measure the thermal performance in terms of thermal resistance from cold-plate base to inlet liquid and obtain 15 mm2 K/W at 30 kPa pressure drop across the package. We build two different topologies using silicon cold-plates and injection-molded lids. Gasket-attached cold-plates pass an 800 kPa pressure test, and direct-attached cold-plates fracture in the cold-plate. The results advise to use a compliant layer between cold-plate and manifold lid and promise a uniformly thick TIM1 layer in the Si–Si matched topology. The work shows the feasibility of composite lids with integrated silicon cold-plates in high heat flux applications.