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All-digital TX frequency synthesizer and discrete-time receiver for bluetooth radio in 130-nm CMOS

TLDR
In this paper, the authors present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process, which is compatible with digital deep-submicron CMOS processes and can be readily integrated with a digital baseband and application processor.
Abstract
We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm 2 and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

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Citations
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All-Digital I/Q RF-DAC

S.M. Alavi
TL;DR: This thesis proposes a wideband, high-resolution, all-digital orthogonal I/Q radio-frequency digital-to-analog (RF-DAC), which is discussed that contemporary RF transceivers must support most of multi-mode/multiband communication standards such as Wi-Fi, Bluetooth, and Fourth Generation (4G) of 3GPP cellular.
Journal ArticleDOI

A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs

TL;DR: An efficient Voltage-Controlled-Oscillator (VCO)–based analog-to-digital converter (ADC) design is proposed to improve the performance and energy efficiency of the CiM architecture and can tolerate ≈30% variability with a negligible impact on the performance of the ADC.
DissertationDOI

Projeto de LNAs CMOS para radiofrequência usando programação geométrica.

TL;DR: This dissertation proposes the design of CMOS narrowband and wideband low noise amplifiers and a topology for wideband LNAs is designed including the geometric programming in an early stage of the design.
Journal ArticleDOI

A 3rd-Order FIR Filter Implementation Based on Time-Mode Signal Processing

TL;DR: In this paper , a 3rd-order low-pass finite impulse response (FIR) filter based on time-mode signal processing circuits was implemented in a 28 nm Samsung fully-depleted silicon-on-insulator FD-SOI process under 1 V supply voltage with 5 MHz sampling frequency.
Dissertation

Digital Phase Locked Loops for Radio Frequency Synthesis

Ahmed Mahmoud
TL;DR: Several IC design techniques are demonstrated, which improve the DPLL in terms of both overall architecture and individual subblocks, which much better exploit the new silicon ecosystems.
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All-digital PLL and transmitter for mobile phones

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Journal ArticleDOI

A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation

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