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Algorithms for VLSI Physical Design Automation
TLDR
This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.Abstract:
From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.read more
Citations
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Journal ArticleDOI
Recent directions in netlist partitioning: a survey
TL;DR: This survey describes research directions in netlist partitioning during the past two decades in terms of both problem formulations and solution approaches, and discusses methods which combine clustering with existing algorithms (e.g., two-phase partitioning).
Journal ArticleDOI
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
Davide Bertozzi,A. Jalabert,Srinivasan Murali,R. Tamhankar,Stergios Stergiou,Luca Benini,G. De Micheli +6 more
TL;DR: This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler).
Book ChapterDOI
Graphs and Digraphs
TL;DR: For the list object, introduced in Chapter 5, it was shown that each data element contains at most one predecessor element and one successor element, so for any given data element or node in the list structure, the authors can talk in terms of a next element and a previous element.
Book ChapterDOI
Spanning Trees and Spanners
TL;DR: This work surveys results in geometric network design theory, including algorithms for constructing minimum spanning trees and low-dilation graphs.
Proceedings ArticleDOI
SUNMAP: a tool for automatic topology selection and generation for NoCs
Srinivasan Murali,G. De Micheli +1 more
TL;DR: SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs and explores various design objectives such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints.
References
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Proceedings ArticleDOI
An immunity based genetic algorithm and its application to the VLSI floorplan design problem
TL;DR: A new algorithm called immunity based GA (IGA) combining features of the immune system (IS) with GA is proposed, expected to have local search ability and prevent premature convergence.
Proceedings ArticleDOI
Standard Cell Placement Using Simulated Sintering
TL;DR: This paper proposes a simulated sintering technique which is analogous to the sintered process in material processing, and shows that by starting out with a good initial configuration instead of a random configuration, and restricting uphill moves, this can considerably speed up simulated annealing.
Proceedings ArticleDOI
An Over-Cell Gate Array Channel Router
TL;DR: A gate array router that utilizes horizontal and vertical over-cell routing channels to increase cell density and Logic macros, with fixed intraconnect metal that may span several cell columns, are mapped onto the array producing partially filled routing channels.
Book ChapterDOI
The Separation for General Single-Layer Wiring Barriers
Alan Siegel,Danny Dolev +1 more
TL;DR: This paper gives efficient algorithms for finding the separation and the offset in contexts which include Tompa's model to solve the single layer routing problem.
Journal ArticleDOI
A provably good multilayer topological planar routing algorithm in IC layout designs
TL;DR: A provably good approximation algorithm for the multilayer topological planar routing problem is presented and experimental results confirm that the algorithm can always route a majority of the nets without using vias, even when the number of routing layers is fairly small.