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Algorithms for VLSI Physical Design Automation
TLDR
This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.Abstract:
From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.read more
Citations
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Journal ArticleDOI
Recent directions in netlist partitioning: a survey
TL;DR: This survey describes research directions in netlist partitioning during the past two decades in terms of both problem formulations and solution approaches, and discusses methods which combine clustering with existing algorithms (e.g., two-phase partitioning).
Journal ArticleDOI
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
Davide Bertozzi,A. Jalabert,Srinivasan Murali,R. Tamhankar,Stergios Stergiou,Luca Benini,G. De Micheli +6 more
TL;DR: This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler).
Book ChapterDOI
Graphs and Digraphs
TL;DR: For the list object, introduced in Chapter 5, it was shown that each data element contains at most one predecessor element and one successor element, so for any given data element or node in the list structure, the authors can talk in terms of a next element and a previous element.
Book ChapterDOI
Spanning Trees and Spanners
TL;DR: This work surveys results in geometric network design theory, including algorithms for constructing minimum spanning trees and low-dilation graphs.
Proceedings ArticleDOI
SUNMAP: a tool for automatic topology selection and generation for NoCs
Srinivasan Murali,G. De Micheli +1 more
TL;DR: SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs and explores various design objectives such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints.
References
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Proceedings ArticleDOI
CAF: A Computer-Assisted Floorplanning Tool
TL;DR: The heuristics used to compute estimated wire lengths and channel congestions are presented and will be shown to be quite accurate.
Journal ArticleDOI
VLSI design automation: An introduction
TL;DR: This paper is a brief introduction to the automation of the design of very-large-scale integrated circuits (VLSI).
Journal ArticleDOI
A new triple-layer OTC channel router
Jaewon Kim,Sung-Mo Kang +1 more
TL;DR: The proposed algorithm for a triple-layer over-the-cell (OTC) routing in an irregular cell area is applied to route MCNC benchmark circuits and Deutsch's difficult problem resulting in a significant reduction in channel area.
Proceedings ArticleDOI
Two-dimensional layout compaction by simulated annealing
T.M. Hsieh,H.W. Leong,C.L. Liu +2 more
TL;DR: An algorithm for the two-dimensional compaction problem or VLSI layouts is presented and the experimental results indicate that the proposed compaction algorithm is quite effective.
Journal ArticleDOI
Switch box routing: a retrospective
TL;DR: The problems which make switch box routing so difficult are discussed and an overview of representative heuristics for solving it is given.