Open AccessBook
Algorithms for VLSI Physical Design Automation
TLDR
This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.Abstract:
From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.read more
Citations
More filters
Journal ArticleDOI
Recent directions in netlist partitioning: a survey
TL;DR: This survey describes research directions in netlist partitioning during the past two decades in terms of both problem formulations and solution approaches, and discusses methods which combine clustering with existing algorithms (e.g., two-phase partitioning).
Journal ArticleDOI
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
Davide Bertozzi,A. Jalabert,Srinivasan Murali,R. Tamhankar,Stergios Stergiou,Luca Benini,G. De Micheli +6 more
TL;DR: This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler).
Book ChapterDOI
Graphs and Digraphs
TL;DR: For the list object, introduced in Chapter 5, it was shown that each data element contains at most one predecessor element and one successor element, so for any given data element or node in the list structure, the authors can talk in terms of a next element and a previous element.
Book ChapterDOI
Spanning Trees and Spanners
TL;DR: This work surveys results in geometric network design theory, including algorithms for constructing minimum spanning trees and low-dilation graphs.
Proceedings ArticleDOI
SUNMAP: a tool for automatic topology selection and generation for NoCs
Srinivasan Murali,G. De Micheli +1 more
TL;DR: SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs and explores various design objectives such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints.
References
More filters
Journal ArticleDOI
An r-Dimensional Quadratic Placement Algorithm
TL;DR: In this paper, the problem of placing n connected points (or nodes) in r-dimensional Euclidean space is given, and the criterion for optimality is minimizing a weighted sum of squared distances between the points subject to quadratic constraints of the form X′X = 1, for each of the r unknown coordinate vectors.
Journal ArticleDOI
Efficient Algorithms for Channel Routing
Takeshi Yoshimura,Ernest S. Kuh +1 more
TL;DR: Two new algorithms merge nets instead of assigning horizontal tracks to individual nets to route a specified net list between two rows of terminals across a two-layer channel in the layout design of LSI chips.
Proceedings Article
The Timber Wolf Placement and Routing Package
TL;DR: TimberWolf as discussed by the authors is an integrated set of placement and routing optimization programs for standard cell, macro/custom cell, and gate-array placement, as well as standard cell global routing.
Journal ArticleDOI
A Procedure for Placement of Standard-Cell VLSI Circuits
A.E. Dunlop,B.W. Kernighan +1 more
TL;DR: A method of automatic placement for standard cells (polycells) that yields areas within 10-20 percent of careful hand placements is described, based on graph partitioning to identify groups of modules that ought to be close to each other.
Journal ArticleDOI
Simple formulas for two- and three-dimensional capacitances
Takayasu Sakurai,K. Tamaru +1 more
TL;DR: In this article, simple formulas for wiring capacitances in VLSI, including two-and/or three-dimensional effects, were proposed for a wide range of wire thickness, wire width, and interwire spacing.