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Algorithms for VLSI Physical Design Automation
TLDR
This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.Abstract:
From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.read more
Citations
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Journal ArticleDOI
Recent directions in netlist partitioning: a survey
TL;DR: This survey describes research directions in netlist partitioning during the past two decades in terms of both problem formulations and solution approaches, and discusses methods which combine clustering with existing algorithms (e.g., two-phase partitioning).
Journal ArticleDOI
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
Davide Bertozzi,A. Jalabert,Srinivasan Murali,R. Tamhankar,Stergios Stergiou,Luca Benini,G. De Micheli +6 more
TL;DR: This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler).
Book ChapterDOI
Graphs and Digraphs
TL;DR: For the list object, introduced in Chapter 5, it was shown that each data element contains at most one predecessor element and one successor element, so for any given data element or node in the list structure, the authors can talk in terms of a next element and a previous element.
Book ChapterDOI
Spanning Trees and Spanners
TL;DR: This work surveys results in geometric network design theory, including algorithms for constructing minimum spanning trees and low-dilation graphs.
Proceedings ArticleDOI
SUNMAP: a tool for automatic topology selection and generation for NoCs
Srinivasan Murali,G. De Micheli +1 more
TL;DR: SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs and explores various design objectives such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints.
References
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Proceedings ArticleDOI
Integrated VLSI layout compaction and wire balancing on a shared memory multiprocessor: evaluation of a parallel algorithm
TL;DR: It is argued that if the MNDS method is used then integrated layout compaction and wire balancing will achieve minimum chip width and a total wire length close to the optimum achieved by the wire balancing algorithm.
Journal ArticleDOI
Algorithms for minimum-bend single row routing problem
TL;DR: It is proved that the maximum number of doglegs per net is bounded by O(k), where k is the size of the maximum clique in a certain graph representing the problem.
Proceedings ArticleDOI
An interactive man-machine approach to the computer logic partitioning problem
M. Hanan,A. Mennone,P. K. Wolff +2 more
TL;DR: An interactive approach which combines aspects of both approaches and creates results which are better than those obtainable by either approach independently is described.
Journal ArticleDOI
Optimal Graph Constraint Reduction for Symbolic Layout Compaction
TL;DR: This work proposes a new formulation of graph constraint reduction in which the maximum possible reduction is guaranteed and presents a polynomial-time algorithm for the new formulation.
Proceedings ArticleDOI
Optimizing wiring space in slicing floorplans
J.T. Mowchenko,Y. Yang +1 more
TL;DR: This paper addresses the problem of minimizing wiring space in an existing slicing floorplan with an exact branch and bound algorithm and a heuristic that are effective in reducing wired space in routed layouts.