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Algorithms for VLSI Physical Design Automation
TLDR
This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.Abstract:
From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.read more
Citations
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Journal ArticleDOI
Recent directions in netlist partitioning: a survey
TL;DR: This survey describes research directions in netlist partitioning during the past two decades in terms of both problem formulations and solution approaches, and discusses methods which combine clustering with existing algorithms (e.g., two-phase partitioning).
Journal ArticleDOI
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
Davide Bertozzi,A. Jalabert,Srinivasan Murali,R. Tamhankar,Stergios Stergiou,Luca Benini,G. De Micheli +6 more
TL;DR: This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler).
Book ChapterDOI
Graphs and Digraphs
TL;DR: For the list object, introduced in Chapter 5, it was shown that each data element contains at most one predecessor element and one successor element, so for any given data element or node in the list structure, the authors can talk in terms of a next element and a previous element.
Book ChapterDOI
Spanning Trees and Spanners
TL;DR: This work surveys results in geometric network design theory, including algorithms for constructing minimum spanning trees and low-dilation graphs.
Proceedings ArticleDOI
SUNMAP: a tool for automatic topology selection and generation for NoCs
Srinivasan Murali,G. De Micheli +1 more
TL;DR: SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs and explores various design objectives such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints.
References
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Proceedings ArticleDOI
Multi-way FPGA partitioning by fully exploiting design hierarchy
Wen-Jong Fang,Allen C.-H. Wu +1 more
TL;DR: This method first synthesizes a design specification in a fine-grained way so that functional clusters can be preserved based on the structural nature of the design specification and applies a hierarchical set-covering partitioning method to form the final FPGA partitionings.
Proceedings ArticleDOI
On minimal closure constraint generation for symbolic cell assembly
Debaprosad Dutt,Chi-Yuan Lo +1 more
TL;DR: An algorithm is presented that generates significantly less closure constraints than O@’ (’) for symbolic layout cell abstraction and the size of the reduced set has been found to be I c-p.
Journal Article
A Compaction Method for Full Chip VLSI Layouts Partitioning Compaction
TL;DR: An algorithm independent layout compaction method for full chip layouts is proposed, which cuts up a large layout, compacts each block independently and then merges them to give the final compacted layout.
Journal ArticleDOI
On single row routing
S. Saxena,V.C. Prasad +1 more
TL;DR: A parallel algorithm for the single-row routing problem without backward moves and interstreet crossings is presented and is modified to run sequentially in O(N) time.
Proceedings ArticleDOI
Macro block based FPGA floorplanning
J. Shi,A. Randhar,Dinesh Bhatia +2 more
TL;DR: The approach is to construct a floorplan of small area that respects the input constraint set that is derived from topological placement of the macro blocks based on both FPGA architectural constraints and ASIC design.