Open AccessBook
Algorithms for VLSI Physical Design Automation
TLDR
This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.Abstract:
From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.read more
Citations
More filters
Journal ArticleDOI
Recent directions in netlist partitioning: a survey
TL;DR: This survey describes research directions in netlist partitioning during the past two decades in terms of both problem formulations and solution approaches, and discusses methods which combine clustering with existing algorithms (e.g., two-phase partitioning).
Journal ArticleDOI
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
Davide Bertozzi,A. Jalabert,Srinivasan Murali,R. Tamhankar,Stergios Stergiou,Luca Benini,G. De Micheli +6 more
TL;DR: This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler).
Book ChapterDOI
Graphs and Digraphs
TL;DR: For the list object, introduced in Chapter 5, it was shown that each data element contains at most one predecessor element and one successor element, so for any given data element or node in the list structure, the authors can talk in terms of a next element and a previous element.
Book ChapterDOI
Spanning Trees and Spanners
TL;DR: This work surveys results in geometric network design theory, including algorithms for constructing minimum spanning trees and low-dilation graphs.
Proceedings ArticleDOI
SUNMAP: a tool for automatic topology selection and generation for NoCs
Srinivasan Murali,G. De Micheli +1 more
TL;DR: SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs and explores various design objectives such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints.
References
More filters
Journal ArticleDOI
Effective buffer insertion of clock tree for high-speed VLSI circuits
Bo Wu,Naveed A. Sherwani +1 more
TL;DR: An effective buffer insertion algorithm for high speed clock layout to minimize the clock delay and skew, based on a new interconnection delay model, in which several practical factors such as crossunders and vias are considered in the delay calculation.
Journal ArticleDOI
Fast algorithm for optimal layer assignment
TL;DR: In this article, the authors proposed a new algorithm for optimal layer assignment under a general model where the planar graph has real-valued edge weights, which has a time complexity of O(n 3 2 log n) where n is the number of wire-segment clusters in a given layout.
Reduction of Clock Delays in VSLI Structures
TL;DR: A tree delay model is developed and is used to determine the optimal number and placement of buffers within the tree so that the clock delay is minimized, and this minimization technique yielded an order of magnitude delay reduction over standard single exponential buffer usage.
Proceedings ArticleDOI
An efficient approach to multi-layer layer assignment with application to via minimization
Chin-Chih Chang,Jason Cong +1 more
TL;DR: An efficient heuristic algorithm for the layer assignment and via minimization problem formulti-layer gridless IC, PCB, and MCM layout and introduces the notion of the extended conflict-continuation (ECC)graph to represent the multi-layer layer assignment problem.