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Algorithms for VLSI Physical Design Automation
TLDR
This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.Abstract:
From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.read more
Citations
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Journal ArticleDOI
Recent directions in netlist partitioning: a survey
TL;DR: This survey describes research directions in netlist partitioning during the past two decades in terms of both problem formulations and solution approaches, and discusses methods which combine clustering with existing algorithms (e.g., two-phase partitioning).
Journal ArticleDOI
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
Davide Bertozzi,A. Jalabert,Srinivasan Murali,R. Tamhankar,Stergios Stergiou,Luca Benini,G. De Micheli +6 more
TL;DR: This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler).
Book ChapterDOI
Graphs and Digraphs
TL;DR: For the list object, introduced in Chapter 5, it was shown that each data element contains at most one predecessor element and one successor element, so for any given data element or node in the list structure, the authors can talk in terms of a next element and a previous element.
Book ChapterDOI
Spanning Trees and Spanners
TL;DR: This work surveys results in geometric network design theory, including algorithms for constructing minimum spanning trees and low-dilation graphs.
Proceedings ArticleDOI
SUNMAP: a tool for automatic topology selection and generation for NoCs
Srinivasan Murali,G. De Micheli +1 more
TL;DR: SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs and explores various design objectives such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints.
References
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Journal ArticleDOI
A Simple Yet Effective Technique for Global Wiring
TL;DR: An implementation for global wiring of a structured custom chip design style is described along with results, and various parameters can be set to give preference to short routes or to reduce the time taken by the algorithm.
Journal ArticleDOI
Efficient Algorithms for Layer Assignment Problem
K.C. Chang,David H. C. Du +1 more
TL;DR: The layer assignment problem for interconnect is the problem of determining which layers should be used for wiring the signal nets and an efficient algorithm for identifying essential vias is presented and discussed in this paper.
Journal ArticleDOI
Global wire routing in two-dimensional arrays
Richard M. Karp,Frank Thomson Leighton,Ronald L. Rivest,Clark D. Thompson,Umesh Vazirani,Vijay V. Vazirani +5 more
TL;DR: A central result of this paper is a “rounding algorithm” for obtaining integral approximations to solutions of linear equations for matrix A and real vector x.
Proceedings ArticleDOI
A “GGreedy” channel router
TL;DR: A new, "greedy", channel-router that always succeeds, usually using no more than one track more than required by channel density, and may occasionally add a new track to the channel to avoid "getting stuck".
Proceedings ArticleDOI
An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints
Yuh-Zen Liao,C. K. Wong +1 more
TL;DR: This paper proposes an algorithm which uses a graph-theoretic approach to solve efficiently the compaction problem with mixed constraints.