Open AccessBook
Algorithms for VLSI Physical Design Automation
TLDR
This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.Abstract:
From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.read more
Citations
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Journal ArticleDOI
Recent directions in netlist partitioning: a survey
TL;DR: This survey describes research directions in netlist partitioning during the past two decades in terms of both problem formulations and solution approaches, and discusses methods which combine clustering with existing algorithms (e.g., two-phase partitioning).
Journal ArticleDOI
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
Davide Bertozzi,A. Jalabert,Srinivasan Murali,R. Tamhankar,Stergios Stergiou,Luca Benini,G. De Micheli +6 more
TL;DR: This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler).
Book ChapterDOI
Graphs and Digraphs
TL;DR: For the list object, introduced in Chapter 5, it was shown that each data element contains at most one predecessor element and one successor element, so for any given data element or node in the list structure, the authors can talk in terms of a next element and a previous element.
Book ChapterDOI
Spanning Trees and Spanners
TL;DR: This work surveys results in geometric network design theory, including algorithms for constructing minimum spanning trees and low-dilation graphs.
Proceedings ArticleDOI
SUNMAP: a tool for automatic topology selection and generation for NoCs
Srinivasan Murali,G. De Micheli +1 more
TL;DR: SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs and explores various design objectives such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints.
References
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Journal ArticleDOI
Unconstrained via minimization for topological multilayer routing
TL;DR: In this article, the minimum number of vias required for realizable multilayer channel routing under a topological model is determined in O(kn/sup 2/ ) time.
Proceedings ArticleDOI
Pin Assignment on a Printed Circuit Board
TL;DR: A method of solving the pin assignment problem that achieves routability of the board by reducing prospective wire crossings is described.
Proceedings ArticleDOI
Cluster refinement for block placement
TL;DR: An iterative optimization approach for mixed macro-cell and standard-cell placement, which minimizes the chipsize and interconnection wire length at the same time and achieves very competitive results to manual design is proposed.
Proceedings Article
Clock distribution scheme for non-symmetric VLSI circuits
TL;DR: The authors propose a clock distribution scheme that minimizes the difference in the length of clock lines, which is the foremost factor responsible for clock skew in a VLSI circuit.
Book
Routing in the Third Dimension : From Vlsi Chips to McMs
TL;DR: This book addresses the algorithmic and cell design issues in chip and MCM routing, with an emphasis on techniques for eliminating routing area, and key features include a wealth of algorithm sover-the-cell (OTC) routing, multi-layer VLSI/thin film MCM routed, and coverage of fabrication-specific issues.