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Algorithms for VLSI Physical Design Automation
TLDR
This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.Abstract:
From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.read more
Citations
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Journal ArticleDOI
Recent directions in netlist partitioning: a survey
TL;DR: This survey describes research directions in netlist partitioning during the past two decades in terms of both problem formulations and solution approaches, and discusses methods which combine clustering with existing algorithms (e.g., two-phase partitioning).
Journal ArticleDOI
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
Davide Bertozzi,A. Jalabert,Srinivasan Murali,R. Tamhankar,Stergios Stergiou,Luca Benini,G. De Micheli +6 more
TL;DR: This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler).
Book ChapterDOI
Graphs and Digraphs
TL;DR: For the list object, introduced in Chapter 5, it was shown that each data element contains at most one predecessor element and one successor element, so for any given data element or node in the list structure, the authors can talk in terms of a next element and a previous element.
Book ChapterDOI
Spanning Trees and Spanners
TL;DR: This work surveys results in geometric network design theory, including algorithms for constructing minimum spanning trees and low-dilation graphs.
Proceedings ArticleDOI
SUNMAP: a tool for automatic topology selection and generation for NoCs
Srinivasan Murali,G. De Micheli +1 more
TL;DR: SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs and explores various design objectives such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints.
References
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Journal ArticleDOI
An Unconstrained Topological Via Minimization Problem for Two-Layer Routing
TL;DR: It is shown that the simplest problem of this type is NP-complete and a heuristic algorithm for topological via minimization is proposed and proposed.
Proceedings ArticleDOI
A heuristic method for FPGA technology mapping based on the edge visibility
TL;DR: An algorithm that assigns visibility values to edges of input Boolean network to minimize the number of nodes in the network is described and compared to the “xl_cover” algorithm provi(ied by the MIS-pga systcm.
Journal ArticleDOI
An algorithm for optimal two-dimensional compaction of VLSI layouts
TL;DR: A branch-and-bound search algorithm that starts with a totally collapsed layout and then removes the distance violations one by one intelligently, keeping only the best legal layout obtained so far is proposed.
Proceedings ArticleDOI
Via Minimization for Gridless Layouts
TL;DR: This paper describes a graph theoretic algorithm which, given a particular layout, finds a layer assignment that requires the minimum number of vias and yields globally optimum results when the maximum junction degree is limited to three and has been fully implemented.