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Algorithms for VLSI Physical Design Automation
TLDR
This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.Abstract:
From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.read more
Citations
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Journal ArticleDOI
Recent directions in netlist partitioning: a survey
TL;DR: This survey describes research directions in netlist partitioning during the past two decades in terms of both problem formulations and solution approaches, and discusses methods which combine clustering with existing algorithms (e.g., two-phase partitioning).
Journal ArticleDOI
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
Davide Bertozzi,A. Jalabert,Srinivasan Murali,R. Tamhankar,Stergios Stergiou,Luca Benini,G. De Micheli +6 more
TL;DR: This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler).
Book ChapterDOI
Graphs and Digraphs
TL;DR: For the list object, introduced in Chapter 5, it was shown that each data element contains at most one predecessor element and one successor element, so for any given data element or node in the list structure, the authors can talk in terms of a next element and a previous element.
Book ChapterDOI
Spanning Trees and Spanners
TL;DR: This work surveys results in geometric network design theory, including algorithms for constructing minimum spanning trees and low-dilation graphs.
Proceedings ArticleDOI
SUNMAP: a tool for automatic topology selection and generation for NoCs
Srinivasan Murali,G. De Micheli +1 more
TL;DR: SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs and explores various design objectives such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints.
References
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Proceedings ArticleDOI
An efficient four layer over-the-cell router
TL;DR: A four layer OTC router which allows arbitrary terminal locations, freed from fixed terminal placement restrictions, so that cell designers can aim to design with minimum width.
Proceedings ArticleDOI
PEPPER-a timing driven early floorplanner
TL;DR: A system for early floorplan analysis of large designs, designed to be used in the early stages of system design, to optimize performance, area and wireability targets before detailed implementation decisions are made.
Journal ArticleDOI
Single-Row Routing with Crossover Bound
TL;DR: This paper develops a fast algorithm for the single-row routing problem when the number of vertical tracks available between adjacent nodes is bounded by a positive integer called the crossover bound and proves that, for any given positive integer K, an instance can be constructed such that the vertical track requirement between adjacent node cannot be less than K.
On the effect of floorplanning on the yield of large area integrated circuits
Zahava Koren,Israel Koren +1 more
TL;DR: In this article, the authors show that the floorplan of a chip can affect its projected yield in a nonnegligible way, for chips with or without fault-tolerance.
Proceedings ArticleDOI
An Efficient Two-Dimensional Layout Compaction Algorithm
Hyunchul Shin,Chi-Yuan Lo +1 more
TL;DR: A new heuristic two-dimensional symbolic layout-compaction approach is developed that generated the smallest area for several examples when compared with other published results.