Open AccessBook
Algorithms for VLSI Physical Design Automation
TLDR
This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.Abstract:
From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.read more
Citations
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Journal ArticleDOI
Recent directions in netlist partitioning: a survey
TL;DR: This survey describes research directions in netlist partitioning during the past two decades in terms of both problem formulations and solution approaches, and discusses methods which combine clustering with existing algorithms (e.g., two-phase partitioning).
Journal ArticleDOI
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
Davide Bertozzi,A. Jalabert,Srinivasan Murali,R. Tamhankar,Stergios Stergiou,Luca Benini,G. De Micheli +6 more
TL;DR: This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler).
Book ChapterDOI
Graphs and Digraphs
TL;DR: For the list object, introduced in Chapter 5, it was shown that each data element contains at most one predecessor element and one successor element, so for any given data element or node in the list structure, the authors can talk in terms of a next element and a previous element.
Book ChapterDOI
Spanning Trees and Spanners
TL;DR: This work surveys results in geometric network design theory, including algorithms for constructing minimum spanning trees and low-dilation graphs.
Proceedings ArticleDOI
SUNMAP: a tool for automatic topology selection and generation for NoCs
Srinivasan Murali,G. De Micheli +1 more
TL;DR: SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs and explores various design objectives such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints.
References
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Book
High ― Level Synthesis: Introduction to Chip and System Design
TL;DR: This paper presents a methodology for High-Level Synthesis of Architectural Models in Synthesis and its applications in Design Description Languages and Design Representation and Transformations.
Journal ArticleDOI
VLSI module placement based on rectangle-packing by the sequence-pair
TL;DR: This paper attacks the biggest MCNC benchmark ami49 with a conventional wiring area estimation method, and obtain a highly promising placement, and proposes a solution space where each packing is represented by a pair of module name sequences, called a sequence-pair.
Journal ArticleDOI
A characterization of comparability graphs and of interval graphs
P. C. Gilmore,Alan J. Hoffman +1 more
TL;DR: In this paper, the authors give a simple algorithm for directing all the edges of a comparability graph in such a way that the resulting graph partially orders its vertices, which they call comparability graphs.
Journal ArticleDOI
Algorithms for Minimum Coloring, Maximum Clique, Minimum Covering by Cliques, and Maximum Independent Set of a Chordal Graph
TL;DR: This paper presents ways for constructing efficient algorithms for finding a minimum coloring, a minimum covering by cliques, a maximum clique, and a maximum independent set given a chordal graph.