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Algorithms for VLSI Physical Design Automation
TLDR
This book is a core reference for graduate students and CAD professionals and presents a balance of theory and practice in a intuitive manner.Abstract:
From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.read more
Citations
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Journal ArticleDOI
Recent directions in netlist partitioning: a survey
TL;DR: This survey describes research directions in netlist partitioning during the past two decades in terms of both problem formulations and solution approaches, and discusses methods which combine clustering with existing algorithms (e.g., two-phase partitioning).
Journal ArticleDOI
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
Davide Bertozzi,A. Jalabert,Srinivasan Murali,R. Tamhankar,Stergios Stergiou,Luca Benini,G. De Micheli +6 more
TL;DR: This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler).
Book ChapterDOI
Graphs and Digraphs
TL;DR: For the list object, introduced in Chapter 5, it was shown that each data element contains at most one predecessor element and one successor element, so for any given data element or node in the list structure, the authors can talk in terms of a next element and a previous element.
Book ChapterDOI
Spanning Trees and Spanners
TL;DR: This work surveys results in geometric network design theory, including algorithms for constructing minimum spanning trees and low-dilation graphs.
Proceedings ArticleDOI
SUNMAP: a tool for automatic topology selection and generation for NoCs
Srinivasan Murali,G. De Micheli +1 more
TL;DR: SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs and explores various design objectives such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints.
References
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Proceedings ArticleDOI
The Complexity of Design Automation Problems
Sartaj Sahni,Atul Bhatt +1 more
TL;DR: This paper reviews several problems that arise in the area of design automation and shows most of them to be NP-hard, pointing out the importance of heuristics and other tools to obtain algorithms that perform well on the problem instances of "interest".
Journal ArticleDOI
SILK: a simulated evolution router
TL;DR: Experimental results showed that SILK, when solving all the benchmarks from the literature, outperformed WEAVER, the most successful switch-box router to date, in both quality and speed aspects.
Journal ArticleDOI
CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design
K. Ueda,H. Kitazawa,I. Harada +2 more
TL;DR: By processing several practical VLSI circuits, it is shown that the method is very effective for handling various kinds of blocks and is able to reduce the design effort required to achieve the chip floor plan.
Proceedings ArticleDOI
A new global router for row-based layout
K.-W. Lee,Carl Sechen +1 more
TL;DR: A global router for row-based layout styles such as sea-of-gates, gate-array, and standard cell circuits is discussed, generalized to handle macro blocks on the chip, equivalent sets of pins, single pins (those without an equivalent), and circuits having many or no built-into-the-cell feeds.
Journal ArticleDOI
Over-the-cell channel routing
Jingsheng Cong,C. L. Liu +1 more
TL;DR: An over-the-cell channel router that produces solutions which are better than the optimal two-layer channel routing solutions for all test examples is designed and outperforms the over- the- cell channel router described by Y. Shiraishi and Y. Sakemi.