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Ambient field effects on the current-voltage characteristics of nanowire field effect transistors

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TLDR
In this paper, the effects of ambient field from the gate and drain contacts on the currentvoltage characteristics of a vertical nanowire field effect transistor having a lightly doped ungated length near the drain were investigated.
Abstract
We investigate the effects of ambient field from the gate and drain contacts on the current-voltage characteristics of a vertical nanowire field effect transistor having a lightly doped ungated length near the drain. Such a device is suitable for high voltage (tens of volts) applications. It is shown that the ambient field enhances the carrier concentration and divides the ungated region into gate-controlled and drain-controlled sections, controllable by the drain contact size and bias-voltages. These phenomena have a significant impact on the drain breakdown voltage, saturation voltage, saturation current and output resistance. The effects are established with the help of measured data and numerically calculated current-voltage curves and field lines.

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Journal ArticleDOI

Vertically integrated silicon-germanium nanowire field-effect transistor

TL;DR: In this article, the possibility to vertically integrate SiGe nanowires in order to use them as vertical channel for field effect transistors (FETs) was demonstrated and a threshold voltage close to 3.9 V was reported.
Journal ArticleDOI

Accelerated Publication: Electrical characteristics of a vertically integrated field-effect transistor using non-intentionally doped Si nanowires

TL;DR: In this paper, the authors report the fabrication and electrical characterization of Vertical Gate All Around Field Effect Transistors (GAA-FET) using nonintentionally doped Silicon NanoWires (SiNWs) grown by Chemical Vapour Deposition (CVD) using the VLS mechanism as conduction channel.
Journal ArticleDOI

All-metal electrodes vertical gate-all-around device with self-catalyzed selective grown InAs NWs array

TL;DR: The first all-metal electrodes vertical gate-allaround (VGAA) FET fabricated using self-catalyzed selective grown InAs NWs array grown by metal organic chemical vapor deposition is reported.
References
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Journal ArticleDOI

Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET

TL;DR: In this paper, the authors presented a vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology, which achieved high aspect ratio (up to 50: 1) vertical nanowires with diameter ~20 nm.
Journal ArticleDOI

Large scale, highly ordered assembly of nanowire parallel arrays by differential roll printing

TL;DR: In this article, a differential roll printing strategy is developed to enable large-scale and uniform assembly of highly aligned and ordered nanowire arrays on various rigid and flexible substrate materials.
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Unusually strong space-charge-limited current in thin wires.

TL;DR: Electronic transport measurements on GaN nanorods are presented and it is shown that poor screening in high-aspect ratio materials leads to a dramatic enhancement of space-charge limited current, resulting in new scaling in terms of the aspect ratio.
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Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor

TL;DR: In this article, a self-aligned n/sup -/ regions are introduced between the channel and the source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity.
Journal ArticleDOI

Experimental evidence of ballistic transport in cylindrical gate-all-around twin silicon nanowire metal-oxide-semiconductor field-effect transistors

TL;DR: In this article, the authors investigated the electrical characteristics of cylindrical gate-all-around twin silicon nanowire metal-oxide-semiconductor field effect transistors with 4nm radius and the gate length ranging from 22to408nm.