Journal ArticleDOI
Ambient field effects on the current-voltage characteristics of nanowire field effect transistors
TLDR
In this paper, the effects of ambient field from the gate and drain contacts on the currentvoltage characteristics of a vertical nanowire field effect transistor having a lightly doped ungated length near the drain were investigated.Abstract:
We investigate the effects of ambient field from the gate and drain contacts on the current-voltage characteristics of a vertical nanowire field effect transistor having a lightly doped ungated length near the drain. Such a device is suitable for high voltage (tens of volts) applications. It is shown that the ambient field enhances the carrier concentration and divides the ungated region into gate-controlled and drain-controlled sections, controllable by the drain contact size and bias-voltages. These phenomena have a significant impact on the drain breakdown voltage, saturation voltage, saturation current and output resistance. The effects are established with the help of measured data and numerically calculated current-voltage curves and field lines.read more
Citations
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Journal ArticleDOI
Vertically integrated silicon-germanium nanowire field-effect transistor
TL;DR: In this article, the possibility to vertically integrate SiGe nanowires in order to use them as vertical channel for field effect transistors (FETs) was demonstrated and a threshold voltage close to 3.9 V was reported.
Journal ArticleDOI
Accelerated Publication: Electrical characteristics of a vertically integrated field-effect transistor using non-intentionally doped Si nanowires
TL;DR: In this paper, the authors report the fabrication and electrical characterization of Vertical Gate All Around Field Effect Transistors (GAA-FET) using nonintentionally doped Silicon NanoWires (SiNWs) grown by Chemical Vapour Deposition (CVD) using the VLS mechanism as conduction channel.
Journal ArticleDOI
All-metal electrodes vertical gate-all-around device with self-catalyzed selective grown InAs NWs array
TL;DR: The first all-metal electrodes vertical gate-allaround (VGAA) FET fabricated using self-catalyzed selective grown InAs NWs array grown by metal organic chemical vapor deposition is reported.
References
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Journal ArticleDOI
Silicon Vertically Integrated Nanowire Field Effect Transistors
TL;DR: In this paper, the authors demonstrate the direct vertical integration of Si nanowire arrays into surrounding gate field effect transistors without the need for postgrowth nanowires assembly processes.
Journal ArticleDOI
Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs
TL;DR: In this paper, a simple but powerful evanescent-mode analysis showed that the length /spl lambda/ over which the source and drain perturb the channel potential, is 1/spl pi/ of the effective device thickness in the double-gate case, and 1/4.810 of the cylindrical case, in excellent agreement with PADRE device simulations.
Journal ArticleDOI
Silicon-Nanowire Transistors with Intruded Nickel-Silicide Contacts
Walter M. Weber,Lutz Geelhaar,A. P. Graham,Eugen Unger,Georg S. Duesberg,Maik Liebau,Werner Pamler,Caroline Chèze,Henning Riechert,Paolo Lugli,Franz Kreupl +10 more
TL;DR: Schottky barrier field effect transistors based on individual catalytically-grown and undoped Si-nanowires (NW) have been fabricated and characterized with respect to their gate lengths, and the transistors displayed p-type behaviour, sustained current densities, and on/off current ratios.