Ambient field effects on the current-voltage characteristics of nanowire field effect transistors

Vertically integrated silicon-germanium nanowire field-effect transistor

Abstract: We demonstrate in this paper the possibility to vertically integrate SiGe nanowires in order to use them as vertical channel for field-effect transistors (FETs). We report a threshold voltage close to 3.9 V, an ION/IOFF ratio of 104. The subthreshold slope was estimated to be around 0.9 V/decade and explained by a high traps density at the nanowire core/oxide shell interface with an estimated density of interface traps Dit ∼ 1.2 × 1013 cm−2 eV−1. Comparisons are made with both vertical Si and horizontal SiGe FETs performances.

Accelerated Publication: Electrical characteristics of a vertically integrated field-effect transistor using non-intentionally doped Si nanowires

Abstract: In this paper, we report the fabrication and the electrical characterization of Vertical Gate All Around Field-Effect Transistors (GAA-FET) using nonintentionally doped Silicon NanoWires (SiNWs) grown by Chemical Vapour Deposition (CVD) using the Vapour-Liquid-Solid (VLS) mechanism as conduction channel. The SiNWs GAA-FET devices exhibited n-channel type semiconductor behaviour whereas the as-grown SiNW FET present p-type behaviour. This effect may be due to positive fixed charge located in the oxide shell or at the Si/SiO"2 interface. Moreover we show that the threshold voltage at room temperature is around -0.95V, a high I"O"N/I"O"F"F ratio up to 10^6 with a low I"O"F"F current about 1pA, a maximum transconductance (g"m","m"a"[email protected] at V"G"S=-0.65V and V"D"S=1V) and a minimum inverse subthreshold slope around 145mV/decade. In light of these characteristics, these devices can be suitable for high performance, low power consumption components and especially for high density integration in integrated circuits (ICs) interconnections regarding to their 3D architecture.

All-metal electrodes vertical gate-all-around device with self-catalyzed selective grown InAs NWs array

Abstract: With the scaling down of field-effect transistors (FETs) to improve their performance, 3D vertical surrounding gate structure has drawn great attention. On the other hand, concerning the channel materials, InAs nanowires (NWs) have been demonstrated to have great potential in FET due to their high mobility and other excellent electrical properties. Here, we report the first all-metal electrodes vertical gate-allaround (VGAA) FET fabricated using self-catalyzed selective grown InAs NWs array grown by metal organic chemical vapor deposition. A typical transistor we fabricated has an on-state current larger than 37 μA/μm when the drain voltage and gate voltage are +0.6 V and +3.0 V, respectively, and an on-off ratio over 3 orders of magnitudes. We have measured 34 transistors in total, and most of them have the on-off ratio between 102 and 104. Annealing is observed to improve the contact property, increase the on-state current, but decrease the on-off ratio. The ways to improve the performance of InAs NW VGAA FET are discussed.

Silicon Vertically Integrated Nanowire Field Effect Transistors

Abstract: Silicon nanowires have received considerable attention as transistor components because they represent a facile route toward sub-100-nm single-crystalline Si features. Herein we demonstrate the direct vertical integration of Si nanowire arrays into surrounding gate field effect transistors without the need for postgrowth nanowire assembly processes. The device fabrication allows Si nanowire channel diameters to be readily reduced to the 5-nm regime. These first-generation vertically integrated nanowire field effect transistors (VINFETs) exhibit electronic properties that are comparable to other horizontal nanowire field effect transistors (FETs) and may, with further optimization, compete with advanced solid-state nanoelectronic devices.

Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs

Abstract: Short-channel effects in fully-depleted double-gate (DG) and cylindrical, surrounding-gate (Cyl) MOSFETs are governed by the electrostatic potential as confined by the gates, and thus by the device dimensions. The simple but powerful evanescent-mode analysis shows that the length /spl lambda/, over which the source and drain perturb the channel potential, is 1//spl pi/ of the effective device thickness in the double-gate case, and 1/4.810 of the effective diameter in the cylindrical case, in excellent agreement with PADRE device simulations. Thus for equivalent silicon and gate oxide thicknesses, evanescent-mode analysis indicates that Cyl-MOSFETs can be scaled to 35% shorter channel lengths than DG-MOSFETs.

Silicon-Nanowire Transistors with Intruded Nickel-Silicide Contacts

Abstract: Schottky barrier field effect transistors based on individual catalytically-grown and undoped Si-nanowires (NW) have been fabricated and characterized with respect to their gate lengths. The gate length was shortened by the axial, self-aligned formation of nickel-silicide source and drain segments along the NW. The transistors with 10−30 nm NW diameters displayed p-type behaviour, sustained current densities of up to 0.5 MA/cm2, and exhibited on/off current ratios of up to 107. The on-currents were limited and kept constant by the Schottky contacts for gate lengths below 1 μm, and decreased exponentially for gate lengths exceeding 1 μm.