Comparative Study of Logic Performance of Hybrid CMOSFETs at Deca-Nanometer Regime

TLDR: In this paper, a comparative analysis is carried out to study the digital circuit behavior of hybrid p-Ge/n-Si CMOSFETs, p-Si/N-InGaAs CMOSFsETs as well as conventional Si CMOS devices at channel length of 60, 30, and 20 nm.

Abstract: A comparative analysis is carried out to study the digital circuit behavior of hybrid p-Ge/n-Si CMOSFETs, p-Si/n-InGaAs CMOSFETs as well as conventional Si CMOS devices at channel length of 60, 30, and 20 nm. Extensive numerical investigation is used to investigate the performance of the different inverter circuits in terms of noise margin low and high, rise and fall times alongside propagation delay. Our studies show that hybrid CMOSFET comprising Si nMOS and Ge pMOS devices performs the best with respect to noise margin high (NMH), noise margin low (NML), and rise time (tr) compared to the hybrid CMOSET comprising InGaAs nMOS and Si pMOS devices and the conventional CMOSFET. However, n-InGaAs/p-Si CMOSFET yields the lowest value of fall time (tf) and time delay per inverter (td) in relation to the values found in other two inverters. Our investigation reveals that all the time parameters for both hybrid CMOSFETs show reduced value compared to the conventional Si counterpart while noise margins show improvement for Si CMOSFETs.