Comparative Study of Logic Performance of Hybrid CMOSFETs at Deca-Nanometer Regime
01 Jan 2021-pp 459-467
TL;DR: In this paper, a comparative analysis is carried out to study the digital circuit behavior of hybrid p-Ge/n-Si CMOSFETs, p-Si/N-InGaAs CMOSFsETs as well as conventional Si CMOS devices at channel length of 60, 30, and 20 nm.
Abstract: A comparative analysis is carried out to study the digital circuit behavior of hybrid p-Ge/n-Si CMOSFETs, p-Si/n-InGaAs CMOSFETs as well as conventional Si CMOS devices at channel length of 60, 30, and 20 nm. Extensive numerical investigation is used to investigate the performance of the different inverter circuits in terms of noise margin low and high, rise and fall times alongside propagation delay. Our studies show that hybrid CMOSFET comprising Si nMOS and Ge pMOS devices performs the best with respect to noise margin high (NMH), noise margin low (NML), and rise time (tr) compared to the hybrid CMOSET comprising InGaAs nMOS and Si pMOS devices and the conventional CMOSFET. However, n-InGaAs/p-Si CMOSFET yields the lowest value of fall time (tf) and time delay per inverter (td) in relation to the values found in other two inverters. Our investigation reveals that all the time parameters for both hybrid CMOSFETs show reduced value compared to the conventional Si counterpart while noise margins show improvement for Si CMOSFETs.
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TL;DR: In this paper, the effect of reduction of ultrathin TiO2 by Ti and its effect on Fermi level depinning and contact resistivity reduction to Si is experimentally studied.
Abstract: Experimental evidence of reduction of ultrathin TiO2 by Ti is presented and its effect on Fermi level depinning and contact resistivity reduction to Si is experimentally studied. A low effective barrier height of 0.15 V was measured with a Ti/10 A TiO2−x/n-Si MIS device, indicating 55% reduction compared to a metal/n-Si control contact. Ultra-low contact resistivity of 9.1 × 10−9 Ω-cm2 was obtained using Ti/10 A TiO2−x/n+ Si, which is a dramatic 13X reduction from conventional unannealed contacts on heavily doped Si. Transport through the MIS device incorporating the effect of barrier height reduction and insulator conductivity as a function of insulator thickness is comprehensively analyzed and correlated with change in contact resistivity. Low effective barrier height, high substrate doping, and high conductivity interfacial layer are identified as key requirements to obtain low contact resistivity using MIS contacts.
143 citations
TL;DR: In this article, the most aggressive dimensions reported in Ge-channel transistors are pMOSFETs with 30-nm gate length on ultrathin germanium-on-insulator substrates (TGe = 25 nm).
Abstract: We present in this letter the most aggressive dimensions reported to date in Ge-channel transistors: pMOSFETs with 30-nm gate length on ultrathin germanium-on-insulator substrates (TGe = 25 nm). By improving both the Ge-enrichment technique and the transistor fabrication process, we demonstrate devices with controlled threshold voltage (Vth) and excellent short-channel effects. Moreover, the low defectivity and the very low thickness of the Ge film lead to a record drain OFF-state leakage for Ge-channel devices (< 1 nA/?m at VDS = -1 V) and thus, to the best ON-state to OFF-state current ratio (ION/IOFF ~5 × 105), even at Lg = 55 nm.
121 citations
TL;DR: In this article, simulation of germanium-on-insulator fully-depleted pMOSFETs has been performed from process to device using 2D Silvaco software and compared with experimental results.
Abstract: Simulations of germanium-on-insulator fully-depleted pMOSFET have been performed from process to device using 2D Silvaco software and compared with experimental results. A comprehensive study of these experimental results allows enlightening the specificity of GeOI devices and leads to a good description of electrical output characteristics at low and high drain-to-source voltage and for various gate lengths. More specifically, the adaptation of mobility model from silicon to germanium, a correct description of interface trap densities and a good consideration of leakage current mechanisms are the main challenges addressed in this paper for GeOI pMOSFET simulation.
16 citations
TL;DR: Investigations reveal that the CMOS circuits comprising of p-Ge and n-InGaAs MOSFETs outperform their equally sized Si counterpart and superior performance of Ge/In GaAs-based CMOS is obtained.
Abstract: CMOS circuits built using Ge-channel p-MOSFETs and InGaAs-channel n-MOSFETs have shown promise for high-performance logic applications. In this paper, we investigate for the first time the performance of such circuits using extensive device simulations. The digital performance of a CMOS inverter is evaluated in terms of noise margins, rise time, fall time, and propagation delay. Furthermore, frequency of oscillations of a three-stage ring oscillator is obtained for varying ratio of the channel width of the p- and the n-MOSFETs, respectively (Wp/Wn). Our investigations reveal that the CMOS circuits comprising of p-Ge and n-InGaAs MOSFETs outperform their equally sized Si counterpart. Moreover, superior performance of Ge/InGaAs-based CMOS is obtained for In0.75Ga0.25 As channel with width ratio (Wp/Wn) of 10: 1. Also, Ge/InGaAs CMOS is found to lose its advantages over Si CMOS for $D_{it}$ exceeding 5 × 10 12 eV−1 · cm−2.
16 citations
03 May 2013
TL;DR: Yasuda et al. as discussed by the authors used an ALD Al2O3 gate insulator and Ta metal gate were used for common gate stacks for InGaAs and Ge, which achieved high electron and hole mobility and low hole effective mass.
Abstract: MOSFETs using channel materials with low effective mass have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime [1, 2]. From this viewpoint, attentions have recently been paid to III-V and Ge channels. This is because III-V semiconductors have extremely high electron mobility and low electron effective mass and Ge has extremely high hole mobility and low hole effective mass. Thus, one of the ultimate CMOS structures can be the combination of III-V nMOSFETs and Ge pMOSFETs [1-4]. In order to realize III-V/Ge CMOS, common gate stack and S/D formation technologies are important. Here, an ALD Al2O3 gate insulator and Ta metal gate were used for common gate stacks for InGaAs and Ge. This is because ALD Al2O3 can provide good MOS interfaces with InGaAs as well as Ge with post ECR plasma oxidation [5]. Also, self-align Ni-Ge and Ni-InGaAs [6], which can be formed simultaneously for InGaAs nMOSFETs and Ge pMOSFETs, were used as the metal source/drain (S/D) regions. By utilizing these technologies, we have demonstrated successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs on a same wafer and their superior device performance [7]. In order to realize the integration of IIIV/Ge MOSFETs and examine the feasibility of proposed integration processes, we have bonded III-V substrates with Ge substrates as a preliminary work. InGaAs-on-Ge wafers with 20-, 50-, and 100-nm-thick InGaAs layers were fabricated for integrating InGaAs-OI nMOSFETs and Ge pMOSFETs. The process flow and the fabricated device structure are shown in Fig. 1. Here, we used the Al2O3 BOX layer with plasma post oxidation as the gateinsulator for Ge pMOSFETs. Ni-based metal S/D for both InGaAs and Ge was formed by annealing at 250 oC for 1 min. We have confirmed that the Ni-InGaAs and Ni-Ge metal S/D are successively formed with Ta gate. The top view of the fabricated devices is shown in Fig. 2. We have found good transistor operation in both devices, shown in Fig. 3, High Ion/Ioff ratio of ~10 6 was obtained for InGaAs-OI nMOSFETs. The high electron and hole mobility of 1800 and 260 cm 2 /Vs and the mobility enhancement against Si of 3.5× and 2.3× have been demonstrated for InGaAs-OI nMOSFETs and Ge pMOSFETs, respectively, as shown in Fig. 4. While the present devices still have thick EOT because of the single Al2O3 gate insulator, we have recently realized HfO2/Al2O3 gate stacks with EOT of 1 nm or less for both InGaAs [8] and Ge [9], allowing us to simultaneously satisfy both thin EOT and good MOS interface properties as the common gate stacks. This work was partly supported by a Grant-in-Aid for Scientific Research (No. 23246058) from MEXT, and Innovation Research Project on Nano electronics Materials and Structures, and Research and Development Program for Innovative Energy Efficiency Technology from NEDO. The authors would like to thank Drs. T. Yasuda, T. Maeda, W. Jevasuwan, N. Miyata, Y. Urabe and H. Takagi in AIST, Drs. M. Hata, T. Osada, O. Ichikawa, and N. Fukuhara in Sumitomo Chemical, and Dr. H. Yokoyama in NTT for their collaborations.
13 citations