Journal ArticleDOI
Effect of Copper TSV Annealing on Via Protrusion for TSV Wafer Fabrication
A. Heryanto,A. Heryanto,W. N. Putra,W. N. Putra,A. D. Trigg,S. Gao,Woon-Seong Kwon,Fa Xing Che,X. F. Ang,Jun Wei,Riko I Made,Chee Lip Gan,Kin Leong Pey,Kin Leong Pey +13 more
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TLDR
In this paper, the authors studied the phenomenon of Cu protrusion and microstructural changes during thermal annealing of a TSV wafer, and proposed a model to provide insight into the failure mechanism.Abstract:
Three-dimensional (3D) integrated circuit (IC) technologies are receiving increasing attention due to their capability to enhance microchip function and performance. While current efforts are focused on the 3D process development, adequate reliability of copper (Cu) through-silicon vias (TSVs) is essential for commercial high-volume manufacturing. Annealing a silicon device with copper TSVs causes high stresses in the copper and may cause a “pumping” phenomenon in which copper is forced out of the blind TSV to form a protrusion. This is a potential threat to the back-end interconnect structure, particularly for low-κ materials, since it can lead to cracking or delamination. In this work, we studied the phenomenon of Cu protrusion and microstructural changes during thermal annealing of a TSV wafer. The extruded Cu-TSV was observed using scanning electron microscopy (SEM), 3D profilometry, and atomic force microscopy (AFM). The electron backscatter diffraction (EBSD) technique was employed to study the grain orientation of Cu-TSV and evolution of the grain size as a function of annealing temperature. The elastic modulus and yield stress of copper were characterized using nanoindentation. A model for Cu protrusion is proposed to provide insight into the failure mechanism. The results help to solve a key TSV-related manufacturing yield and reliability challenge by enabling high-throughput TSV fabrication for 3D IC integration.read more
Citations
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Journal ArticleDOI
Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV)
Wen Wei Shen,Kuan-Neng Chen +1 more
TL;DR: 3D integration with through-silicon via (TSV) is a promising candidate to perform system-level integration with smaller package size, higher interconnection density, and better performance.
Journal ArticleDOI
Study on Cu Protrusion of Through-Silicon Via
TL;DR: In this paper, a finite element analysis (FEA) is carried out to study the Cu protrusion under different annealing conditions and correlation between numerical results and experimental data is then carried out.
Journal ArticleDOI
Plasticity mechanism for copper extrusion in through-silicon vias for three-dimensional interconnects
Tengfei Jiang,Chenglin Wu,Laura Spinella,Jang-Hi Im,Nobumichi Tamura,Martin Kunz,Ho Young Son,Byoung Gyu Kim,Rui Huang,Paul S. Ho +9 more
TL;DR: In this paper, a simple analytical model elucidated the role of plasticity during thermal cycling, and finite element analyses were carried out to confirm the plasticity mechanism as well as the effect of the via/Si interface.
Journal ArticleDOI
Through-silicon via stress characteristics and reliability impact on 3D integrated circuits
TL;DR: In this article, the thermal expansion mismatch between copper vias and silicon (Si) can induce complex stresses in TSV structures to drive interfacial failure and Cu extrusion, degrading the performance and reliability of 3D interconnects.
Proceedings ArticleDOI
Impact of post-plating anneal and through-silicon via dimensions on Cu pumping
Joke De Messemaeker,Olalla Varela Pedreira,Bart Vandevelde,Harold Philipsen,Ingrid De Wolf,Eric Beyne,Kristof Croes +6 more
TL;DR: In this paper, the impact of post-plating anneal temperature and time on residual Cu pumping during a sinter for 20 min at 420 °C, for two different TSV dimensions using optical profilometry, in total ~ 4000 TSVs were measured.
References
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