Journal ArticleDOI
Efficient Modeling of Power Supply Induced Jitter in Voltage-Mode Drivers (EMPSIJ)
TLDR
In this paper, an efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented, based on separating the large signal response and the small signal noise response and subsequently combining the results.Abstract:
An efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented. Semianalytical expressions for jitter are derived based on separating the large signal response and the small signal noise response and subsequently combining the results. Proposed simplified relations enable the designers to estimate the PSIJ based on a single bit simulation. Proposed methods are validated on several examples of voltage-mode driver circuits, designed in different technologies and in the presence of different types of noise sources.read more
Citations
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Proceedings ArticleDOI
Jitter Estimation in a CMOS Tapered Buffer for an Application of Clock Distribution Network
TL;DR: This paper presents an analysis and estimation of timing error due to the power supply noise for a five-stage CMOS tapered buffer used in the clock distribution network for the application of successive approximation register (SAR).
Proceedings ArticleDOI
A Practical Estimation of Periodic Power Supply Induced Jitter for Clock Buffer Chains
Warren Anderson,Xiongliang Lai +1 more
TL;DR: The closed-form expression is algebraically simple requiring only a few circuit simulation results without the pre-knowledge of circuit SPICE parameters and predicts MOS clock buffer’s period PSIJ and N-Cycle PSIJ.
Proceedings ArticleDOI
Analysis of PSIJ in the presence of both ground-bounce and transmission media
TL;DR: A semi-analytical method is presented to estimate the PSIJ in the presence of both the transmission media as well as the ground bounce, and while providing comparable accuracy yields significant speed-up.
Proceedings ArticleDOI
Extension of EMPSIJ for Estimating the Impact of Substrate Noise on Jitter in a CMOS Inverter
TL;DR: In this article, the authors present an analysis of jitter in a CMOS inverter due to power supply, ground bounce and substrate noise, and the results match reasonably well with mean percentage error (MPE) not exceeding 10%.
Journal ArticleDOI
Analytical Modeling of Deterministic Jitter in CMOS Inverters
TL;DR: In this paper , an analytical approach is presented which estimates jitter in CMOS inverters in the presence of power supply noise (PSN), data noise (DN), and ground-bounce noise (GBN) by deriving analytical relationships.
References
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Book
The Fourier Transform and Its Applications
TL;DR: In this paper, the authors provide a broad overview of Fourier Transform and its relation with the FFT and the Hartley Transform, as well as the Laplace Transform and the Laplacian Transform.
Journal ArticleDOI
The Fourier Transform and Its Applications
Book
Jitter, Noise, and Signal Integrity at High-Speed
TL;DR: The fundamental terminology, definitions, and concepts associated with JNB and SI, as well as their sources and root causes are introduced, and Dr. Li provides powerful new tools for solving these problems quickly, efficiently, and reliably.
Related Papers (5)
Propagation Delay-Based Expression of Power Supply-Induced Jitter Sensitivity for CMOS Buffer Chain
Xin Jie Wang,Tad Kwasniewski +1 more