Efficient Modeling of Power Supply Induced Jitter in Voltage-Mode Drivers (EMPSIJ)

A Review on Power Supply Induced Jitter

Abstract: The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented from the basics of power delivery networks to PSN and eventually to the modeling of PSIJ. The in-depth details and a review of several methodologies available in the literature for the estimation of PSIJ are presented.

Efficient Jitter Analysis for a Chain of CMOS Inverters

Abstract: This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy.

Fast Analysis of Time Interval Error in Current-Mode Drivers

Abstract: An efficient approach for modeling of time interval error (TIE) due to noise in power delivery networks (PDNs), for current-mode (CM) driver circuits, is presented. Semianalytical expressions relating the PDN noise and TIE are developed based on midpoint delays of the rising and falling edges of the differential signal. The validating examples with CM driver circuits designed in various technologies comparing both the proposed and conventional approaches demonstrate a significant speedup using the proposed approach.

An Efficient Estimation of Power Supply-Induced Jitter by Numerical Method

Abstract: This letter presents an efficient and generic methodology for the estimation of power supply-induced jitter by the numerical method using a root-finding approach. The methodology is described in detail through an example of a voltage-mode driver circuit. There is a significant speed-up reported compared with the simulations by a commercial simulator.

Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator

Abstract: This paper presents the timing error and power supply induced jitter (PSIJ) analyses of an inverter based high-speed comparator, including the design of common-mode body biasing feedback circuitry. Both the main circuit and the supporting circuitry have been designed and implemented in a standard 28 nm CMOS technology with power supply of 0.9 V. The closed-form transfer function of the comparator including biasing circuitry, used in PSIJ analysis, is derived using symbolic admittance method. The mathematical model shows an agreement with the simulation and exhibits 7.4% of mean percentage error (MPE).

The Fourier Transform and Its Applications

Abstract: 1 Introduction 2 Groundwork 3 Convolution 4 Notation for Some Useful Functions 5 The Impulse Symbol 6 The Basic Theorems 7 Obtaining Transforms 8 The Two Domains 9 Waveforms, Spectra, Filters and Linearity 10 Sampling and Series 11 The Discrete Fourier Transform and the FFT 12 The Discrete Hartley Transform 13 Relatives of the Fourier Transform 14 The Laplace Transform 15 Antennas and Optics 16 Applications in Statistics 17 Random Waveforms and Noise 18 Heat Conduction and Diffusion 19 Dynamic Power Spectra 20 Tables of sinc x, sinc2x, and exp(-71x2) 21 Solutions to Selected Problems 22 Pictorial Dictionary of Fourier Transforms 23 The Life of Joseph Fourier

Jitter, Noise, and Signal Integrity at High-Speed

Abstract: State-of-the-art JNB and SI Problem-Solving: Theory, Analysis, Methods, and ApplicationsJitter, noise, and bit error (JNB) and signal integrity (SI) have become today's greatest challenges in high-speed digital design. Now, there's a comprehensive and up-to-date guide to overcoming these challenges, direct from Dr. Mike Peng Li, cochair of the PCI Express jitter standard committee.One of the field's most respected experts, Li has brought together the latest theory, analysis, methods, and practical applications, demonstrating how to solve difficult JNB and SI problems in both link components and complete systems. Li introduces the fundamental terminology, definitions, and concepts associated with JNB and SI, as well as their sources and root causes. He guides readers from basic math, statistics, circuit and system models all the way through final applications. Emphasizing clock and serial data communications applications, he covers JNB and SI simulation, modeling, diagnostics, debugging, compliance testing, and much more.Coverage includes? JNB component classification, interrelationships, measurement references, and transfer functions Statistical techniques and signal processing theory for quantitatively understanding and modeling JNB and related components Jitter, noise, and BER: physical/mathematical foundations and statistical signal processing views Jitter separation methods in statistical distribution, time, and frequency domains Clock jitter in detail: phase, period, and cycle-to-cycle jitter, and key interrelationships among them PLL jitter in clock generation and clock recovery Jitter, noise, and SI mechanisms in high-speed link systems Quantitative modeling and analysis for jitter, noise, and SI Testing requirements and methods for links and systems Emerging trends in high-speed JNB and SI As data rates continue to accelerate, engineers encounter increasingly complex JNB and SI problems. In Jitter, Noise, and Signal Integrity at High-Speed, Dr. Li provides powerful new tools for solving these problemsi??quickly, efficiently, and reliably.Preface xvAcknowledgements xxiAbout the Author xxiiiChapter 1: Introduction 1Chapter 2: Statistical Signal and Linear Theory for Jitter, Noise, and Signal Integrity 27Chapter 3: Source, Mechanism, and Math Model for Jitter and Noise 75Chapter 4: Jitter, Noise, BER (JNB), and Interrelationships 109Chapter 5: Jitter and Noise Separation and Analysis in Statistical Domain 131Chapter 6: Jitter and Noise Separation and Analysis in the Time and Frequency Domains 163Chapter 7: Clock Jitter 185Chapter 8: PLL Jitter and Transfer Function Analysis 209Chapter 9: Jitter and Signal Integrity Mechanisms for High-Speed Links 253Chapter 10: Modeling and Analysis for Jitter and Signaling Integrity for High-Speed Links 281Chapter 11: Testing and Analysis for Jitter and Signaling Integrity for High-Speed Links 309Chapter 12: Book Summary and Future Challenges 345Index 353