Proceedings ArticleDOI
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test
V. R. Devanathan,C.P. Ravikumar,V. Kamakoti +2 more
- pp 167-172
TLDR
The authors show that glitching activity on nodes must be considered in order to correctly handle constraints on instantaneous peak power and include a power profiler that can analyze a pattern source for violations and a PODEM-based pattern generation engine for generating power-safe patterns.Abstract:
Excessive dynamic voltage drop in the power supply rails during test mode is known to result in false failures and impact yield when testing devices that use low-cost wire-bond packages. Identifying and debugging such test failures is a complex and effort-intensive process, especially when scan compression is involved. From a design cycle-tune view point, it is best to avoid this problem by generating "power-safe" scan patterns. The generation of power-safe patterns must take into consideration the DFT architecture, physical design, tuning and power constraints. In this paper, the authors propose such a framework and show experimental results on some benchmark circuits. The framework can address a non-uniform power grid and region-based power constraints. The authors show that glitching activity on nodes must be considered in order to correctly handle constraints on instantaneous peak power. The framework includes a power profiler that can analyze a pattern source for violations and a PODEM-based pattern generation engine for generating power-safe patterns.read more
Citations
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Proceedings ArticleDOI
Power-aware test: Challenges and solutions
TL;DR: Concerns and challenges in power-aware test are highlighted, various practices drawn from both academia and industry are surveyed, and critical gaps that need to be addressed in the future are pointed out.
Proceedings ArticleDOI
Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing
TL;DR: This work is the first to solve the yield loss caused by excessive power supply noise in at-speed scan testing by proposing a novel integrated ATPG scheme that efficiently and effectively performs compressible X-filling.
Proceedings ArticleDOI
Capture power reduction using clock gating aware test generation
TL;DR: By taking advantage of the existing clock gating circuitry and selectively holding the value of some scan flip-flops, switching activity during the capture cycles of a test can be reduced.
Proceedings ArticleDOI
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification
Kohei Miyase,Kenji Noda,Hideaki Ito,Kazumi Hatayama,Takashi Aikyo,Yuta Yamato,Hiroshi Furukawa,Xiaoqing Wen,Seiji Kajihara +8 more
TL;DR: A novel test relaxation method, called Distribution-Controlling X-Identification (DC-XID), which controls the distribution of X-bits identified from a set of fully-specified test vectors for the purpose of effectively reducing IR-drop is proposed.
Proceedings ArticleDOI
Improved weight assignment for logic switching activity during at-speed test pattern generation
TL;DR: In this article, a new weight assignment scheme for logic switching activity was proposed, which enhances the IR-drop assessment capability of the existing weighted switching activity (WSA) model by including the power grid network structure information.
References
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Journal ArticleDOI
Low-power scan design using first-level supply gating
TL;DR: A novel circuit technique to virtually eliminate test power dissipation in combinational logic by masking signal transitions at the logic inputs during scan shifting by inserting an extra supply gating transistor in the supply to ground path for the first-level gates at the outputs of the scan flip-flops.
Proceedings ArticleDOI
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TL;DR: This work proposes an effective method for applying fine-delay fault testing in order to improve defect coverage of especially resistive opens by grouping conventional delay-fault patterns into sets of almost equal-length paths, which narrows the overall path length distribution and allows running the pattern sets at a higher speed, thus enabling the detection of small delay faults.
Proceedings ArticleDOI
A new ATPG method for efficient capture power reduction during scan testing
Xiaoqing Wen,Seiji Kajihara,Kohei Miyase,Tatsuya Suzuki,Kewal K. Saluja,Laung-Terng Wang,Khader S. Abdel-Hafez,Kozo Kinoshita +7 more
TL;DR: Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation.
Proceedings ArticleDOI
On reducing peak current and power during test
TL;DR: Experimental results show that the proposed method reduces the peak current and power dissipation during the fast capture cycle by 40.59% on average and up to 54.17% for large ISC AS 89 circuits.
Journal ArticleDOI
Compact physical IR-drop models for chip/package co-design of gigascale integration (GSI)
K. Shakeri,James D. Meindl +1 more
TL;DR: In this article, the tradeoff between on-chip interconnect dimensions and the number of I/O pads required for power distribution is quantified for chip/package co-design.