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Journal ArticleDOI

Optimization of NCFET by Matching Dielectric and Ferroelectric Nonuniformly Along the Channel

TLDR
In this paper, a new design to overcome the nonuniformity of capacitance matching along the channel of a negative capacitance field effect transistor is presented, in which the thickness of SiO2 at the edge regions of the channel can be increased while maintaining the thickness at the center region.
Abstract
A new design to overcome the nonuniformity of capacitance matching along the channel of a negative capacitance field-effect transistor is presented in this letter. By introducing nonuniform oxidation, the thickness of SiO2 at the edge regions of the channel can be increased while maintaining the thickness of SiO2 at the center region of the channel. As a result, the capacitance along the channel becomes more uniform, and better capacitance matching between the dielectric and ferroelectric can be achieved. The Sentaurus TCAD results show improvement of matching in the center region and a significant boost of ON-current (20% improvement).

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Citations
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Journal ArticleDOI

Effect of different capacitance matching on negative capacitance FDSOI transistors

TL;DR: It is observed that NCFETs with a two-layer ferroelectric structure can effectively adopt the capacitance matching in different operation regions, thereby increasing the on- state current and reducing the off-state current, resulting in higher switching current ratio (ION/IOFF) than the single-layer counterpart.
Journal ArticleDOI

A review of III-V Tunnel Field Effect Transistors for future ultra low power digital/analog applications

TL;DR: This article highlights the scalability of III-V TFETs, influence of thickness and permittivity of gate dielectric, interface trap density, other geometrical dimensions, material properties and various TFET architectures on the ON and OFF state performance ofIII-VTFETs.
Journal ArticleDOI

A Junctionless Accumulation Mode NC-FinFET Gate Underlap Design for Improved Stability and Self-Heating Reduction

TL;DR: In this article, a metal ferroelectric insulator semiconductor (MFIS) -type junctionless accumulation mode (JAM) negative capacitance (NC)-FinFET with reduced self-heating is proposed for the low-power Internet-of-Things (IoT) applications at 7-nm technology node.
Journal ArticleDOI

Negative capacitance enables GAA scaling VDD to 0.5 V

TL;DR: It is shown that the NC-FinFET can be scaled to "2.1nm node" and almost "1.5nm node", which is the last FinFET node according to the International Roadmap for Devices and Systems (IRDS).
References
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Journal ArticleDOI

Nanoelectronics: negative capacitance to the rescue?

TL;DR: Can ferroelectric materials help transistors overcome the 'Boltzmann tyranny' that limits the performances of conventional semiconductor devices?
Proceedings ArticleDOI

14nm Ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications

TL;DR: In this paper, Doped hafnia ferroelectric layers with thicknesses from 3 to 8nm are integrated into state-of-the-art 14nm FinFET technology without any further process modification.
Journal ArticleDOI

Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics

TL;DR: In this article, the effect of the variation of ferroelectric material properties (thickness, polarization, and coercivity) on the performance of negative capacitance FETs was studied.
Journal ArticleDOI

Multidomain ferroelectricity as a limiting factor for voltage amplification in ferroelectric field-effect transistors

TL;DR: In this article, Salahuddin and Datta showed that the negative-capacitance regime that allows for such amplification is actually bounded by the appearance of multidomain ferroelectricity.
Journal ArticleDOI

On the stabilization of ferroelectric negative capacitance in nanoscale devices

TL;DR: This work presents a comprehensive revision of the theory of NC stabilization with respect to scaling of material and device dimensions based on multi-domain Ginzburg-Landau theory and proposes downscaling of lateral device dimensions to prevent domain formation and to enhance the voltage amplification due to NC.
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