Journal ArticleDOI
Optimization of NCFET by Matching Dielectric and Ferroelectric Nonuniformly Along the Channel
Ming-Yen Kao,Yen-Kai Lin,Harshit Agarwal,Yu-Hung Liao,Pragya Kushwaha,Avirup Dasgupta,Sayeef Salahuddin,Chenming Hu +7 more
TLDR
In this paper, a new design to overcome the nonuniformity of capacitance matching along the channel of a negative capacitance field effect transistor is presented, in which the thickness of SiO2 at the edge regions of the channel can be increased while maintaining the thickness at the center region.Abstract:
A new design to overcome the nonuniformity of capacitance matching along the channel of a negative capacitance field-effect transistor is presented in this letter. By introducing nonuniform oxidation, the thickness of SiO2 at the edge regions of the channel can be increased while maintaining the thickness of SiO2 at the center region of the channel. As a result, the capacitance along the channel becomes more uniform, and better capacitance matching between the dielectric and ferroelectric can be achieved. The Sentaurus TCAD results show improvement of matching in the center region and a significant boost of ON-current (20% improvement).read more
Citations
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Journal ArticleDOI
Effect of different capacitance matching on negative capacitance FDSOI transistors
TL;DR: It is observed that NCFETs with a two-layer ferroelectric structure can effectively adopt the capacitance matching in different operation regions, thereby increasing the on- state current and reducing the off-state current, resulting in higher switching current ratio (ION/IOFF) than the single-layer counterpart.
Journal ArticleDOI
Implementation and Performance Evaluation of Ferroelectric Negative Capacitance FET
Journal ArticleDOI
A review of III-V Tunnel Field Effect Transistors for future ultra low power digital/analog applications
TL;DR: This article highlights the scalability of III-V TFETs, influence of thickness and permittivity of gate dielectric, interface trap density, other geometrical dimensions, material properties and various TFET architectures on the ON and OFF state performance ofIII-VTFETs.
Journal ArticleDOI
A Junctionless Accumulation Mode NC-FinFET Gate Underlap Design for Improved Stability and Self-Heating Reduction
TL;DR: In this article, a metal ferroelectric insulator semiconductor (MFIS) -type junctionless accumulation mode (JAM) negative capacitance (NC)-FinFET with reduced self-heating is proposed for the low-power Internet-of-Things (IoT) applications at 7-nm technology node.
Journal ArticleDOI
Negative capacitance enables GAA scaling VDD to 0.5 V
TL;DR: It is shown that the NC-FinFET can be scaled to "2.1nm node" and almost "1.5nm node", which is the last FinFET node according to the International Roadmap for Devices and Systems (IRDS).
References
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Journal ArticleDOI
Intrinsic speed limit of negative capacitance transistors
TL;DR: In this paper, the authors established a coherent theoretical framework to analyze the delay between the clock edge at the gate and the response of the semiconductor channel in a ferroelectric negative capacitance transistor.
Journal ArticleDOI
Switching-Speed Limitations of Ferroelectric Negative-Capacitance FETs
Zhi Cheng Yuan,Shahriar Rizwan,Michael Wong,Kyle D. Holland,Sam Anderson,Terence B. Hook,Diego Kienle,Serag Gadelrab,Prasad S. Gudem,Mani Vaidyanathan +9 more
TL;DR: In this paper, the authors investigated the high-frequency switching behavior of negative-capacitance FETs using the Landau-Khalatnikov equation to model ferroelectric materials.
Journal ArticleDOI
Work Function Engineering for Performance Improvement in Leaky Negative Capacitance FETs
TL;DR: In this paper, the effects of ferroelectric leakage on the performance of a negative capacitance field effect transistor (NCFET) have been analyzed, which has an intermediate metallic layer between the Ferroelectric and the high-K dielectric.
Journal ArticleDOI
Hysteresis Reduction in Negative Capacitance Ge PFETs Enabled by Modulating Ferroelectric Properties in HfZrO x
Jiuren Zhou,Yue Peng,Genquan Han,Qinglong Li,Yan Liu,Jincheng Zhang,Min Liao,Qing-Qing Sun,David Wei Zhang,Yichun Zhou,Yue Hao +10 more
TL;DR: In this article, the post annealing temperature of negative capacitance (NC) Ge pFETs is modulated to increase the ratio of remnant polarization to coercive field in HfZrO x (HZO).
Proceedings ArticleDOI
Hysteresis-free negative capacitance germanium CMOS FinFETs with Bi-directional Sub-60 mV/dec
TL;DR: In this article, the first hysteresis-free Ge CMOS FinFETs exhibiting sub-60 mV/dec subthreshold slope (SS) in both forward and reverse sweeps at room temperature were reported on 10 nm Hf 05 Zr 05 O 2 (HZO) Ge pFinFET Ferroelectric (FE) HZO film is integrated with Al 2 O 3 /GeOx as a gate stack.
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