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Journal ArticleDOI

Physics-based capacitance model of Gate-on-Source/Channel SOI TFET

Suman Mitra, +1 more
- 01 Dec 2018 - 
- Vol. 13, Iss: 12, pp 1672-1676
TLDR
A surface potential-based analytical capacitance model is proposed for gate-on-source–channel silicon on insulator (SOI) tunnel field effect transistor (GOSC TFET) and a good agreement between the modelled andTCAD simulated surface potential leads to the accurate calculation of capacitance.
Abstract
A surface potential-based analytical capacitance model is proposed for gate-on-source–channel silicon on insulator (SOI) tunnel field effect transistor (GOSC TFET) The capacitance in the GOSC TFET is evidently shared by the gate-to-source capacitance which reduces the miller capacitance and leads to better switching speed in the circuit application The effect of drain voltage, gate voltage, gate oxide thickness and source doping on the capacitance has been analysed in detail The good matching between the modelled and Technology Computer-Aided Design (TCAD) simulated surface potential leads to the accurate calculation of capacitance The validation of the capacitance model is done by comparing the model result with the simulation result and a good agreement between them validates the model formulation

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Citations
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Journal ArticleDOI

Analytical model of a novel double gate metal-infused stacked gate-oxide tunnel field-effect transistor (TFET) for low power and high-speed performance

TL;DR: In this paper, a double gate tunnel field effect transistor (TFET) is proposed with a channel length of 20nm and the gate dielectric regions have been renovated by inserting metal strips and using stacked gate-oxide concept.
Journal ArticleDOI

Lower subthreshold swing and improved miller capacitance heterojunction tunneling transistor with overlapping gate

TL;DR: In this article, gate oxide overlapping technique is implemented in heterojunctions to obtain better sub-threshold swing, high ON state current and improved miller capacitance for beyond-CMOS technologies.
Journal ArticleDOI

Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

TL;DR: In this article, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software.

Gate-on-Source TFET Analytical Model: Role of Mobile Charges and Depletion Regions

TL;DR: In this paper, a 2D analytical model for the double gate tunnel FET (DG-TFET) is presented, which considers the gate-on-source overlap that may occur intentionally or unintentionally due to fabrication tolerances.
References
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Journal ArticleDOI

Tunnel field-effect transistors as energy-efficient electronic switches

TL;DR: Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Journal ArticleDOI

Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Journal ArticleDOI

Device scaling limits of Si MOSFETs and their application dependencies

TL;DR: The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.
Journal ArticleDOI

Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric

TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI

A literature survey on smart cities

TL;DR: The origin and main issues facing the smart city concept are introduced, and the fundamentals of a smart city by analyzing its definition and application domains are presented.
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Trending Questions (1)
Why the value of gate to source capacitance lowers with gate voltage?

The value of gate-to-source capacitance lowers with gate voltage due to the reduction in the miller capacitance.