Journal ArticleDOI
The Impact of Fringing Field on the Device Performance of a p-Channel Tunnel Field-Effect Transistor With a High- $\kappa$ Gate Dielectric
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In this article, the effects of varying the dielectric constant κ of the gate dielectrics on the device performance of a p-channel tunnel field effect transistor (p-TFET) was investigated.Abstract:
Detailed investigation, with the help of extensive device simulations, of the effects of varying the dielectric constant κ of the gate dielectric on the device performance of a p-channel tunnel field-effect transistor (p-TFET) is reported for the first time in this paper It is observed that the fringing field arising out of a high-κ gate dielectric degrades the device performance of a p-TFET, which is in contrast with its n-channel counterpart of a similar structure, where the same has been reported to yield better performance The impact of the fringing field is found to be larger for a p-TFET with higher source doping It is also found that the qualitative nature of the impact of the fringing field does not change with dimension scaling On the other hand, the higher electric field due to increased oxide capacitance is found to be beneficial for a p-TFET when a high- κ gate dielectric is used in it, as expected It is also found that a low- κ spacer is beneficial for a p-TFET, similar to that reported for an n-TFET of similar structureread more
Citations
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Journal ArticleDOI
Tunnel Field-Effect Transistors for Analog/Mixed-Signal System-on-Chip Applications
TL;DR: In this article, the analog performance of a double-gate n-type tunnel field effect transistor (n-TFET) with a relatively small body thickness (10 nm) was investigated.
Journal ArticleDOI
An Analytical Model for Tunnel Barrier Modulation in Triple Metal Double Gate TFET
Navjeet Bagga,Subir Kumar Sarkar +1 more
TL;DR: An analytical model for tunnel barrier modulation in triple metal double gate tunnel FET is presented for the first time in this paper, where three different metals over the channel region assist to form a barrier in the channel which restricts the reverse tunneling of the carrier, i.e., tunneling from drain to source.
Journal ArticleDOI
Impact of a Spacer–Drain Overlap on the Characteristics of a Silicon Tunnel Field-Effect Transistor Based on Vertical Tunneling
TL;DR: In this article, a detailed investigation of the effects of a spacer-drain overlap on the device characteristics of such silicon TFETs is reported, and it is demonstrated that a supersteep subthreshold swing and a significantly reduced off-state current IOFF can be achieved by appropriate designing of the spacer drain overlap.
Journal ArticleDOI
An Analytical Modeling and Simulation of Dual Material Double Gate Tunnel Field Effect Transistor for Low Power Applications
TL;DR: In this article, a new two dimensional analytical modeling and simulation for a dual material double gate tunnel field effect transistor (DMDG TFET) is proposed and the results show a significant improvement in on-current characteristics while short channel effects are greatly reduced.
Journal ArticleDOI
Improved performance of nanoscale junctionless tunnel field-effect transistor based on gate engineering approach
TL;DR: In this paper, the performance characteristics of dual-work function gate junctionless TFET (DWG-JLTFET) on the basis of energy band profile modulation is investigated.
References
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Journal ArticleDOI
Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
Scaling the Si MOSFET: from bulk to SOI to bulk
R.-H. Yan,Abbas Ourmazd,K.F. Lee +2 more
TL;DR: In this article, the scaling of fully depleted SOI devices is considered and the concept of controlling horizontal leakage through vertical structures is highlighted, and several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design.
Journal ArticleDOI
Silicon surface tunnel transistor
TL;DR: A silicon surface tunneling transistor structure, based on lateral band-to-band tunneling, is presented in this article, which is controlled by the bias on the gate of the device which modulates the width of the tunneling barrier.
Journal ArticleDOI
The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs
Baohong Cheng,Min Cao,R. Rao,A. Inani,P. Vande Voorde,Wayne Greene,J.M.C. Stork,Zhiping Yu,P.M. Zeitzoff,Jason C. S. Woo +9 more
TL;DR: In this paper, the potential impact of high/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities using a two-dimensional (2D) simulator implemented with quantum mechanical models.
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