Proceedings ArticleDOI
Thermal analysis of ultra-thin body device scaling [SOI and FinFet devices]
TLDR
In this article, the effect of confined dimensions and complicated geometries on the self-heating of ultra-thin body SOI and FinFET devices is explored, incorporating the most advanced understanding of nanoscale heat conduction available.Abstract:
This paper explores the effect of confined dimensions and complicated geometries on the self-heating of ultra-thin body SOI and FinFET devices A compact thermal model is introduced, incorporating the most advanced understanding of nanoscale heat conduction available Novel device scaling is analyzed from a thermal point of view We show device temperatures are very sensitive to the choice of drain and channel extension dimensions, and suggest a parameter design space which can help alleviate thermal problems ITRS power guidelines below the 25 nm technology node should be revised if isothermal scaling of thin-body devices is desiredread more
Citations
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Journal ArticleDOI
Heat Generation and Transport in Nanometer-Scale Transistors
TL;DR: Trends in transistor geometries and materials, from bulk silicon to carbon nanotubes, along with their implications for the thermal design of electronic systems are surveyed.
Journal ArticleDOI
Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation
TL;DR: In this article, a 2-D drift-diffusion electrothermal simulation, using an electron transport model calibrated against Monte Carlo simulations at various temperatures, is employed to analyze the impact of thermal effects on the operation of nanoscale SOI n-MOSFETs.
Journal ArticleDOI
Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures
Mayank Shrivastava,M. Agrawal,S. Mahajan,Harald Gossner,T. Schulz,Dinesh K. Sharma,Valipe Ramgopal Rao +6 more
TL;DR: In this article, a detailed physical insight on the lattice heating and heat flux in a 3D front end of the line and complex back end of line of a logic circuit network is given for bulk/silicon-on-insulator (SOI) FinFET and extremely thin SOI devices using 3-D TCAD.
Journal ArticleDOI
Fully Coupled Nonequilibrium Electron–Phonon Transport in Nanometer-Scale Silicon FETs
TL;DR: In this paper, a detailed heat generation and transport mechanism in silicon devices with a focus on the nonequilibrium behavior of electrons and phonons is discussed, and fully coupled and self-consistent ballistic phonon and electron simulations are developed in order to examine the departure from equilibrium within the phonon system and its relevance for properly simulating the electrical behavior of devices.
Journal ArticleDOI
Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability
TL;DR: A rigorous analytical thermal model has been formulated for the analysis of self-heating effects in FinFETs, under both steady-state and transient stress conditions, which is critical for improving circuit performance and electrical overstress/electrostatic discharge (ESD) reliability.
References
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Thermal boundary resistance
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TL;DR: In this article, the thermal boundary resistance at interfaces between helium and solids (Kapitza resistance) and thermal boundary resistances at interfaces interfaces between two solids are discussed for temperatures above 0.1 K. The apparent qualitative differences in the behavior of the boundary resistance in these two types of interfaces can be understood within the context of two limiting models of boundary resistance, the acoustic mismatch model, which assumes no scattering, and the diffuse mismatch model that all phonons incident on the interface will scatter.
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Heat transport in thin dielectric films
Seungmin Lee,David G. Cahill +1 more
TL;DR: In this article, heat transport in 20-300 nm-thick dielectric films is characterized in the temperature range of 78-400 K using the 3-ω method.
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Phonon scattering in silicon films with thickness of order 100 nm
Y. S. Ju,Kenneth E. Goodson +1 more
TL;DR: In this paper, the authors studied the relaxation times of room-temperature thermal phonons through measurements of thermal conduction along monocrystalline silicon films of thickness down to 74 nm and showed that the effective mean free path of the dominant phonons at room temperature is close to 300 nm and thus much longer than the value of 43 nm predicted when phonon dispersion is neglected.
Journal ArticleDOI
Essential physics of carrier transport in nanoscale MOSFETs
Mark Lundstrom,Zhibin Ren +1 more
TL;DR: In this paper, the physics of charge control, source velocity saturation due to thermal injection, and scattering in ultrasmall MOSFETs are examined. And the results show that the essential physics of nanoscale MOSFLETs can be understood in terms of a conceptually simple scattering model.
Journal ArticleDOI
Thermal conduction in doped single-crystal silicon films
TL;DR: In this paper, the authors measured the thermal conductivities along free-standing silicon layers doped with boron and phosphorus at concentrations ranging from 1×1017 to 3×1019 cm−3 at temperatures between 15 and 300 K.