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Journal ArticleDOI

Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability

TLDR
A rigorous analytical thermal model has been formulated for the analysis of self-heating effects in FinFETs, under both steady-state and transient stress conditions, which is critical for improving circuit performance and electrical overstress/electrostatic discharge (ESD) reliability.
Abstract
A rigorous analytical thermal model has been formulated for the analysis of self-heating effects in FinFETs, under both steady-state and transient stress conditions. 3-D self-consistent electrothermal simulations, tuned with experimentally measured electrical characteristics, were used to understand the nature of self-heating in FinFETs and calibrate the proposed model. The accuracy of the model has been demonstrated for a wide range of multifin devices by comparing it against finite element simulations. The model has been applied to carry out a detailed sensitivity analysis of self-heating with respect to various FinFET parameters and structures, which are critical for improving circuit performance and electrical overstress/electrostatic discharge (ESD) reliability. The transient model has been used to estimate the thermal time constants of these devices and predict the sensitivity of power-to-failure to various device parameters, for both long and short pulse ESD situations. Suitable modifications to the model are also proposed for evaluating the thermal characteristics of production level FinFET (or Tri-gate FET) structures involving metal-gates, body-tied bulk FinFETs, and trench contacts.

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Citations
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Journal ArticleDOI

A Thermal-Aware Device Design Considerations for Nanoscale SOI and Bulk FinFETs

TL;DR: In this article, the thermal performance characteristics of fin-shaped FETs (FinFETs) are studied and analyzed for sub-22-nm technologies using the well-calibrated TCAD simulations.
Journal ArticleDOI

Self-Heating Effect in FDSOI Transistors Down to Cryogenic Operation at 4.2 K

TL;DR: In this paper, the authors demonstrate that below 160 K, the channel temperature increase due to self-heating starts to deviate significantly from the linear variation with the dissipated power, leading to an apparent power dependent thermal resistance.
Proceedings ArticleDOI

Self-heating in advanced CMOS technologies

TL;DR: An overview of the research on self-heating in transistors is presented and modulators, measurement schemes, spatio-temporal sensitivities, and impacts on performance and reliability are discussed.
Journal ArticleDOI

3D Modeling of Spatio-temporal Heat-transport in III-V Gate-all-around Transistors Allows Accurate Estimation and Optimization of Nanowire Temperature

TL;DR: In this article, a 3D electrothermal simulation model is developed to explore and interpret self-heating and heat dissipation in gate-all-around (GAA) devices.
References
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Journal ArticleDOI

Thermal boundary resistance

TL;DR: In this article, the thermal boundary resistance at interfaces between helium and solids (Kapitza resistance) and thermal boundary resistances at interfaces interfaces between two solids are discussed for temperatures above 0.1 K. The apparent qualitative differences in the behavior of the boundary resistance in these two types of interfaces can be understood within the context of two limiting models of boundary resistance, the acoustic mismatch model, which assumes no scattering, and the diffuse mismatch model that all phonons incident on the interface will scatter.
Journal ArticleDOI

Energy dissipation and transport in nanoscale devices

TL;DR: In this article, the authors present recent progress in understanding and manipulation of energy dissipation and transport in nanoscale solid-state structures, including silicon transistors, carbon nanostructures, and semiconductor nanowires.
Journal ArticleDOI

Energy Dissipation and Transport in Nanoscale Devices

TL;DR: In this article, the authors present recent progress in understanding and manipulation of energy dissipation and transport in nanoscale solid-state structures, including silicon transistors, carbon nanostructures, and semiconductor nanowires.
Journal ArticleDOI

Ballistic metal-oxide-semiconductor field effect transistor

TL;DR: In this article, the authors proposed the ballistic transport of carriers in MOSFETs, and presented the currentvoltage characteristics of the ballistic n-channel MOS-FET.
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