Showing papers on "Clock gating published in 1988"

Clock signal supply system

Abstract: A clock signal supply system provides for automatic accurate phase adjustment of clock signals. The system includes an oscillator that produces clock signals and a reference generator that generates a reference signal that has a predetermined relationship with respect to the clock signals produced by the oscillator. At each location where the clock signal is to be received, an adjusting circuit is provided to adjust the phase of the received clock signals. Such an adjusting circuit may include a variable delay circuit which receives the clock signal and produces an output which is constituted by the clock signal having a varied delay, to the remainder of the attached circuits. Further, the output of the variable delay is fed back to a phase difference detection circuit. The reference signal is second input to the phase difference detection circuit. This phase difference detection circuit compares the difference of the reference signal and the output of the variable delay circuit and produces the control signal to the variable delay circuit which will further adjust the phase of the clock signal that is received. This adjustment is carried out at each of the locations where the clock signal is to be received, thereby providing automatic adjustment of the phase of the clock signals.

Clock signal distribution device

Abstract: A delay circit is described which automatically adjusts the propagation delay of clock signals, generated by a clock source, distributed to various receiving devices so that the receiving devices are clocked simultaneously. In one embodiment, the clock signal generated by a single clock source is independently delayed for each receiving device. To determine the proper amount of delay, a clock signal is simultaneously transmitted to each of the receiving devices and a clock return signal from each receiving device is returned to a delay circuit via a return path. The delay circuit detects the various differences in round-trip arrival times of the clock signal associated with each receiving device and fixes a particular clock signal delay for each receiving device so that subsequent clock signals will arrive at each receiving device simultaneoulsy.

An envelope-following method for the efficient transient simulation of switching power and filter circuits

Abstract: The transient behavior of circuits like switching power converters and switched capacitor filters are expensive to simulate because they are clocked at a frequency whose period is orders of magnitude smaller than the time interval of interest to the designer. It is possible to reduce the simulation time without compromising accuracy by exploiting the fact that the behavior of such a circuit in a given high-frequency clock cycle is similar, but not identical, to its behavior in the preceding and following cycles. In particular, the envelope of the high-frequency clock can be followed by accurately computing the circuit behavior over occasional cycles. The authors describe the implementation of an envelope-following method that is particularly efficient for switching power and filter circuits, and they present results demonstrating the method's effectiveness. >

Clock scheme for VLSI systems

Abstract: An integrated circuit includes an input clock generator circuit (10) responsive to an external TTL level clock signal (C1) for generating an internal CMOS level system clock signal (C2) for its own use and for use by other integrated circuits. The integrated circuit also includes an internal clock generator circuit (16) responsive to either the internal CMOS level system clock signal (C2) or an external CMOS level system clock signal (C3) for generating internal CMOS level phase clock signals (0₁, 0₂) for its own use. As a result, the integrated circuit has a higher speed of operation since the propagation delay between the CMOS level system clock signal and internal clock signals has been minimized.

Dynamic latch circuit for preventing short-circuit current from flowing during absence of clock pulses when under test

Abstract: Described herein is a dynamic latch circuit having a pair of control terminals connected to receive complementary first and second control clock pulses which are generated at a predetermined frequency, and a register section for detecting the voltage of an input signal, in response to each of the first and second control clock pulses, and generating an output signal from a capacitive output node which is charged or discharged in accordance with the voltage of the input signal and is subsequently set at a low potential or a high potential. The latch circuit further comprises a voltage-generating circuit for detecting, based on a period of time elapsed from the trailing edge of the last generated first control clock pulse, that the supply of the first control clock pulses has been stopped and fixedly setting the output node at the low potential.

Clock generator which generates a non-overlap clock having fixed pulse width and changeable frequency

Abstract: A clock generator which is cascade connected a plurality of single-phase pulse generator circuits including RS flip-flops and delay circuits for defining the pulse width of one output at the RS flip-flop through gates controlling propagation of the other output of the RS flip-flop, so that the final clock frequency is variable by switching control of each gate, whereby a pulse width of each single-phase clock is defined by a delay duration of a delay circuit, thereby not depending on wave forms of the external clock and also the gates connected between the respective single-phase pulse generating circuits are switching-controlled to enable the frequency of the output clock to be variable.

Transient free clock switch logic

Abstract: The invention provides a circuit for selecting a first clock, disabling a second or additional clocks and positively enabling the selected first clock only after the second or additional clocks no longer provide signal to the circuit.

Method and circuit for controlling single chip microcomputer

Abstract: A clock circuit for a microcomputer having a clock input, a halt mode state output and an interrupt input, comprises: a clock pulse generator having an output, a switch for applying a pulsed output to the interrupt input of the microcomputer to indicate a start of operation; a latch receptive of the output of the switch to change from a first state to a second state, gates receptive of the output of the clock pulse generator and the latch for applying clock pulses to the microcomputer when the logic is in the second state and preventing the application of clock pulses to the microcomputer when the logic is in the first state and circuitry for applying the halt mode state output to the logic circuit to disable same from the second state to the first state.

Bit phase synchronizing circuit

Abstract: PURPOSE: To attain the operation of a spatial split type switch with a common clock by constituting the circuit with a clock frequency divider circuit and an elastic storage of conventional constitution so as to allow a data to take over a clock having a speed of a multiple of N and independent bit phase. CONSTITUTION: A clock frequency divider circuit 2 receives a 2nd clock 3 and outputs the clock while dividing the frequency to 1/N. A clock 1 and a data D synchronously with the clock are inputted to an elastic storage ES. With a clock 3 having a frequency at a multiple of N of the frequency of the clock 1 and independent bit phase received to the circuit 2, the frequency divider circuit 2 divides the clock frequency into the frequency the same as the frequency (1/N) of the clock 1 and the resulting signal is inputted to a terminal C2 of the elastic storage ES as the clock 2. A data synchronously with the clock 2 is outputted from a terminal Q of the elastic storage ES. The output data is naturally synchronously with the clock 3. COPYRIGHT: (C)1990,JPO&Japio

Clock timing controller for a plurality of LSI chips

Abstract: LSI chips are divided into a first chip and a plurality of second chips, and each of the first and second chips has a frequency divider for deriving a lower-frequency output clock signal from a higher-frequency input clock signal. A higher-frequency input clock signal is supplied to the first chip from an external clock source to produce a lower-frequency output clock signal. One of the second chips is selected by a chip selector and its clock output is applied to a phase comparator for comparison with the clock output of the first chip for generating a phase difference signal in response to a phase difference between the compared output clock signals. Gate circuits are enabled in the absence of the phase difference signal to supply the input clock signal to all of the second chips. The chip selector is shifted to the next one of the second chips in response to a chip selection signal in the absence of the phase difference signal. In the presence of a phase difference signal, one of the gate circuits which is associated with the selected chip is disabled to inhibit the application of the clock signal to the LSI chip in which synchronization slippage has occurred.

A safe single-phase clocking scheme for CMOS circuits

Abstract: A single-phase clock has two edges. A clocking scheme utilizing the two edges of a single-phase clock to control the movement of data is presented. The scheme is similar to the two-phase nonoverlapping clocking scheme. A single-phase clock CMOS shift register to illustrate this clocking schemes is proposed. This shift register utilizes the bistable element, 'sense amplifier', to sense the state of its previous stage. There are two stages. The first stage triggers on the rising edge and the second stage triggers on the trailing edge. It is a static register with no minimum clocking frequency. Instead of four clock phases used in conventional CMOS dynamic shift registers, or two clock phases used in existing static registers, only one clock phase is used. This single-phase clocking scheme greatly reduces the overhead of having to route two or four clock signals around the chip. It also eliminated the clock skewing difficulty plaguing the conventional shift register. >

Disk drive clock writer

Abstract: A clock pattern writer for a disk drive, having circuitry to write a preliminary clock pattern having a number of clock pulses approximately equal to a desired predetermined number of clock pulses. A second clock pattern having the predetermined number of clock pulses is written by correcting the preliminary pattern as appropriate to achieve the desired number of clock pulses. In the illustrated embodiment, a phase lock loop generates a source signal in phase with the preliminary clock pattern and correction circuitry repeatedly advances or retards the phase of selected individual pulses of the source signal so that the second clock pattern has the predetermined number of clock pulses. Preferably, phase transients in the clock pattern may be eliminated or reduced by writing a third clock pattern using a phase lock loop locked to the second clock pattern.

Dynamic switching circuit for multiple asynchronous clock sources

Abstract: A dynamic switching circuit for multiple asynchronous clock sources comprising a pair of flip-flops which are set and reset in such a manner as to provide high frequency and low frequency output clock pulses without a glitch and within a period extending from approximately a few nanoseconds to no greater than a period equal to the sum of the periods of one of said high and low frequency clock pulses.

Noise suppression in recovery of clock from NRZ data

Abstract: A clock generator for extracting a clock signal from a data signal includes a timing recovery circuit operable to produce an output recovered clock which is synchronized with transitions occurring at its input. A circuit gates data transitions to the clock recovery circuit input only during time windows defined in a manner based upon the recovered clock. The time windows are produced by comparing the output of an integrator on the recovered clock signal to a reference. The comparator output resets a D-flip flop, to which the data is applied as a clock, the output of the D-flip flop being connected to the input of the timing recovery circuit.

Variable frequency clock pulse generator for microcomputer

Abstract: A clock pulse generator for a one-chip microprocessor permits the microprocessor to be operated on two different power sources by effectively using a single source of clock pulses, a clock pulse divider and gate circuits to gate a specific sequence of pulses to the microprocessor. The period of a slowest clock pulse signal after division is integrally related to the periods of the faster clock pulse signals so that the pulse signals are synchronously provided.

True single phase clock dynamic CMOS circuit technique

Abstract: Some CMOS circuit techniques, based on a true single-phase clock, where the clock is never inverted, are described. Single-phase dynamic logic and single-phase precharge logic circuits are considered. The advantage of this approach is simple and compact clock distribution and high speed. The high-speed possibility was demonstrated with a binary divider. A clock frequency of 160 MHz was achieved when only standard transistors in a 3- mu m CMOS process were used. The single-phase clock is relatively insensitive to clock rise time, clock fall time, and clock skew. >

Dynamic cmos current surge control

Abstract: Integrated circuits having a large number of transmission gate logic stages have been found to draw a large current surge on power-up. This is due to the floating input node of complementary inverters causing current to flow briefly before clock pulses arrive. The present invention provides a DC voltage on the gates of the pass transistors until the system clock pulses arrive, thereby eliminating the floating node. An optional periodic window may be generated to examine the system clock after power-up, to detect a loss of clock condition.

Clock control system

Abstract: A clock control system includes two clock supply units and two data processing units. Each clock supply unit is capable of supplying clock signals at either of two frequencies. The clock control system allows each data processing unit to be supplied with clock signals of either frequency from either clock supply unit. If one clock supply unit becomes defective, any data processing unit being supplied by that one defective clock supply unit can have its clock supply switched to the non-defective clock supply unit, without having to change the frequency of the non-defective clock supply unit.

Circuit for generating non-overlapping two-phase clocks

Abstract: In order to provide for clocking master/slave flip-flops in complex circuits by means of non-overlapping two-phase clocks, a clock generator for providing two clocks signals for use with two-phase flip-flops, comprises a settable latch and a gating device. The settable latch has a data input connected to a reference source, a set input connected to receive one of the two clock signals and a clock input connected to receive the other of the two clock signals. The gating device has one input connected to receive such one of the two clock signals and a second input connected to the output of the settable latch. The output of the gating device, which corresponds to the other of the two clock signals, is connected to the clock input of the settable latch, the arrangement being such that when the settable latch has been set by a transition of the one clock signal resetting of the settable latch is enabled by the other clock signal. A digital circuit, for example an integrated circuit, may have a number of latches, each comprising, for example the first stage of a master/slave flip-flop, and such a clock generator for operating them. Preferably the latches are arranged in groups, conveniently as a macro sub-block, with a clock generator for operating each group. Preferably the settable latch is similar in construction to the latches being controlled.

Circuit for dividing the frequency of a digital clock signal by two and one-half

Abstract: A circuit for dividing a clock signal by two and one-half (2.5) is shown. The divide by two and one-half (2.5) circuit includes a clock selector circuit arranged to output a selected polarity of the first clock signal. A ring counter arranged to receive the clock selector circuit output signal, and output a signal that has a period of 3 times (3×) the signal received from the clock selector circuit. A divide by two circuit connected to the ring counter circuit and to the clock selector circuit. The divide by two circuit divides the ring counter output signal by two to produce an output signal. The divide by two output signal is then fed back to the clock selector circuit to regulate the selection of the first clock signal polarity, causing the ring counter to output a clock signal with a period of two and one-half times (2.5×) the first clock signal.

Clock phase adjusting system

Abstract: A clock phase adjusting system is provided, including: a scan in/our apparatus, having (n+1) special scan-out latch circuits; a first delay device which selectively outputs an input clock as a delay clock output of a maximum m=2 n steps in accordance with an (n) bit selection signal; a second delay device which selectively outputs the input clock signal as the delay clock signals of further minimum 1/2 P steps of a minimum step width by the first delay device in accordance with the (P) bit selection signal and which is connected in cascade with the first delay device, so that the delayed clock signals of 1/2 P steps are output as the input clock signal by only setting, in the (n+p) scan in/out latch circuits, the selection data for obtaining a delay clock signal.

Unconditional clock and automatic refresh logic

Abstract: A novel unconditional clock and automatic refresh logic system is provided which comprises a source of unconditional clock pulses coupled to the memory control logic in a manner which permits automatic refreshing of a dynamic memory. There is further provided clock logic means which sense the conditions in the dynamic memory system during which the dynamic memory is not being refreshed. There is further provided, means for generating automatic clock refresh signals coupled to the memory control logic for initiating continuous automatic refresh cycles when the system clock is being shutdown.

Exchange for a meshed telecommunications network

Abstract: If the exchange selected as master clock generator is taken out of operation in a meshed telecommunications network, the remaining exchanges must look for a new master clock generator. During this search process, each exchange must operate with its own clock source. Since the clock sources of the individual exchanges are now no longer synchronised with one another, this mandatorily leads to information losses when messages are exchanged between the individual exchanges. The newly designed exchange should provide for fast synchronisation of the clock source to a master clock and ensure that the telecommunication network operates as faultlessly as possible in the event of disturbances in the telecommunications network. For this purpose, a clock recovery unit with two outputs is provided in the exchange for each other exchange connected to it, which clock recovery unit outputs at a first output a clock signal regenerated from received data and, in the event of a non-regenerable clock signal, a clock failure signal at a second output; each output can be supplied via a switching means to the clock source, the switching means being controllable by a priority discriminator, and the first outputs of the clock recovery unit are supplied to a synchronisation input of the clock source and the second outputs of the clock recovery unit are supplied to an integration time change-over switch arranged in the clock generator.

Arrangement for monitoring two clock signals in a manner which is reliable in terms of signal technology

Abstract: In order to monitor two clock signals in a manner which is reliable in terms of signal technology against one of them remaining off or drifting away etc., for example in areas of stringent safety requirements, it is proposed that the clock signals (clock 1, clock 2) be offset in time with respect to one another and trigger associated monostable multivibrators (MF1, MF2). The monostable multivibrators (MF1, MF2) generate imaging signals (e1, e2) of defined pulse length which are applied to a non-equivalence comparator (1) which is reliable in signal technology terms and supplies an output signal (AV) which is monitored by a downstream-connected RS memory (2) which is reliable in signal technology terms. The output of said RS memory (2) is connected via amplification means (3, 4), which are reliable in signal technology terms, to a switching element (5) which influences an energy flow or signal flow and is reliable in signal technology terms. In a further embodiment, the clock signals (clock 1, clock 2) are offset equidistantly in time in error-free operation, the imaging signals (e1, e2) of the monostable multivibrators (MF1, MF2) which are triggered by the rising edges of the clock signals (clock 1, clock 2) being at the same interval and having the same pulse length.

Circuit configuration for routine testing of the clock supply of a large number of units operated with the same clock

Abstract: A circuit configuration for the routine testing of the clock supply of a large number of digital TDM telecommunication units operated with the same clock, wherein a clock supply with stand-by generator through a corresponding arrangement of several monitor circuits and arrangements of on/alter switches, the operatability of the monitor circuits themselves can be tested so that on routine testing independent of the switching position of a change-over switching device effective upon switching a generator from stand-by operation to active operation respectively the same generator always acts upon the partial distribution system.

Clock distribution on vlsi chip

Abstract: A VLSI chip has a core logic area with a system clock bus CLB to distribute clock signals to the application specific logic in that area. Clock signals are supplied to the bus via one pin P3, and clock skew (clock pulse distribution delay) is monitored by means of a second pin (P4) connected (at 49) to a point on the bus separated from the connection point of the first pin. Substantially all normal (operational) signals to and from the core logic area are coupled to the chip pins by means of input/output cells located in the peripheral area of the chip.

Method and circuit arrangement for semiconductor devices with highly integrated LSI technique logic gating circuits

Abstract: For subsequently influencing the circuit functions of logic gating circuits (VS) combined in semiconductor chips with highly-integrated ALSI technique, the control inputs (SE) additionally provided at the initial gating elements (AVE) of the logic gating circuit (VS) are activated by means of a preceding, externally adjustable signal allocation arrangement (SZA1) and/or gating arrangement (VA) with control signals which remain unconsidered during the definition of the circuit functions and by means of which, if necessary, circuit functions can be replaced or newly formed in the gating circuits (VS) and errored signals can be corrected. If necessary, the externally and internally available input signals are conducted via a second signal allocation arrangement (SZA2) preceding the gating arrangement (VA) in order to obtain, from a small number of input signals (S), a large number of different signals at different control inputs (SE) of the gating circuits.

Parallel synchronizing circuit

Abstract: PURPOSE: To cause a transfer clock frequency to be close to an operating clock frequency by successively instructing the operation of plural synchronous circuits for reception synchronously to the effective change of a transfer clock and operating the plural synchronous circuits for reception in parallel. CONSTITUTION: An allotment circuit 40 generates and allots allotting signals RXCa and RXCb, whose high levels are not overlapped, synchronously to the effective edge change of a transfer clock RXC with being alternatively changed at every cycle of a transfer clock TXC. One allotting signal RXCa to be generated in this circuit 40 is supplied to a clock input terminal CK of FFs 23 and 27 and the other allotting signal RXCb is supplied to the clock input terminal of FFs 30 and 34. The allotting signals RXCa and RXCb are alternatively controlled to the high level synchronously to the cycle of the transfer clock RXC. Accordingly, the instruction of synchronizing operation to synchronous circuits 21 and 22 is alternatively given at every cycle of the transfer clock RXC. Thus, the respective synchronizing circuits 21 and 22 can define the almost two cycles of the transfer clock RXC as a maximum synchronization operatable period to 1 bit data. COPYRIGHT: (C)1990,JPO&Japio

Multi-phase clock circuitry

Abstract: Circuitry for defining a multi-phase clock having a clock rate determined by a reference clock signal comprises a phase locked loop (15) driven by the reference clock signal. The phase locked loop has feedback path including multi-cell means (21, 23) for providing an accumulated multi-bit adjustment count, and a feed forward path including a plurality of discretely adjustable delay circuit stages (7,9, 11, 13) for producing a plurality of phase-boundary-defining signals under the control of the accumulated adjustment count. The circuitry further comprises circuit means (25) responsive to the phase-boundary-defining signals for producing parallel pulse signals that in combination define the multi-phase clock.

Arrangement for commuting a clock on a clock with the same frequency but lagging in phase

Abstract: At high switching rates, switching processes can become inadequately coordinated in time in integrated switching arrangements. Spikes occurring as a result during switching operations are to be avoided. The switching arrangement consists of control logic (1), a clock monitoring circuit (2) and a clock selector (3). The control logic (1) contains a shift register with register cells (Z1 to Zn) which, apart from the first one, are all identical. The identical cells exhibit a D-type flip flop (H2 to Hn) in which a precontrol signal (St2" to Stn") is formed by temporarily storing a control signal (St1 to Stn-1). In the first register cell (Z1), a precontrol signal (St1") is produced when all others (St2" to Stn") are missing. Switching occurs in dependence on a correction signal (K) and the clocks at the register cells concerned, in such a manner that first the previous control signal is switched off before the new control signal is switched on. In the clock selector (3), the active control signal switches through the associated clock as auxiliary data clock (DHT). The clock monitoring circuit (2) generates a start signal (Sta) when, erroneously, no or simultaneously several control signals have been formed (from St1 to Stn). The arrangement can be used in the clock recovery in digital signal multiplex devices.