Showing papers on "Drain-induced barrier lowering published in 2005"

High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability

Abstract: For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process With 10nm diameter nanowire, saturation currents through twin nanowires of 264 mA/mum, 111 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively No roll-off of threshold voltages, ~70 mV/dec of substhreshold swing (SS), and ~20 mV/V of drain induced barrier lowering(DIBL) down to 30 nm gate length are observed for both n-ch and p-ch TSNWFETs

Split-channel antifuse array architecture

Abstract: Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor. More specifically, the present invention provides an effective method for utilizing split channel MOS structures as an anti-fuse cell suitable for OTP memories.

Self DC-bias high frequency logic gate, high frequency NAND gate and high frequency NOR gate

Abstract: A self DC-bias high frequency logic gate is disclosed. The logic gate comprises at least one input terminal and one output terminal for performing Boolean operation on the high frequency input signals. The logic gate is characterized in that each transistor is coupled to an impedance matching network. The impedance matching network comprises a first terminal and a second terminal. Wherein, the first terminal is coupled to a gate of the transistor, and the second terminal is coupled to a drain of the transistor for providing an operation voltage to the transistor. When a gate of an N-type transistor and a gate of a P-type transistor are coupled with each other, and a drain of the N-type transistor and a drain of the P-type transistor are also coupled with each other, a common impedance matching network is shared with both the N-type transistor and the P-type transistor.

High-performance 50-nm-gate-length Schottky-source/drain MOSFETs with dopant-segregation junctions

Abstract: High-performance operation was achieved in a novel Schottky-source/drain MOSFET (SBT: Schottky barrier transistor), which has dopant-segregation (DS) Schottky source/drain. Sub-100 nm complementary DS-SBTs were fabricated using the CoSi/sub 2/ process, which was fully compatible with the current CMOS technology. Excellent CMOS performance was obtained without any channel-mobility degradation, and CMOS ring oscillator was successfully demonstrated. In addition, >20 % improvement in drive current over the conventional n-MOSFETs was confirmed in the n-type DS-SBTs around the gate length of 50 nm.

Control of threshold voltage of organic field-effect transistors with double-gate structures

Abstract: We fabricated pentacene field-effect transistors with planar-type double-gate structures, where the top- and bottom-gate electrodes can independently apply voltage biases to channel layers. The threshold voltage of organic transistors is changed systematically in a wide range from −16to−43V when the voltage bias of the top-gate electrode is changed from 0to+60V. The mobility in the linear regime is almost constant (0.2cm2∕Vs) at various voltage biases of the top-gate electrode and the on/off ratio is 106.

Semiconductor device and method for fabricating such device

Abstract: An LDMOS transistor and a bipolar transistor with LDMOS structures are disclosed for suitable use in high withstand voltage device applications, among others. The LDMOS transistor includes a drain well region 21 formed in P-type substrate 1, and also formed therein spatially separated one another are a channel well region 23 and a medium concentration drain region 24 having an impurity concentration larger than that of drain well region 21, which are simultaneously formed having a large diffusion depth through thermal processing. A source 11 s is formed in channel well region 23, while a drain 11 d is formed in drain region 24 having an impurity concentration larger than that of drain region 24. In addition, a gate electrode 11 g is formed over the well region, overlying the partially overlapped portions with well region 23 and drain region 24 and being separated from drain 11 d. Since the source 11 s, well region 23, and drain region 24 are respectively self-aligned to the gate electrode 11 g, resultant transistor characteristics are stabilized, and the decrease in the on resistance and improved drain threshold voltages can be achieved. Also disclosed herein are bipolar transistors with LDMOS structures, which are capable of obviating the breakdown of gate dielectric layers even at high applied voltage and achieving improved stability in transistor characteristics.

Field effect transistor and method for manufacturing the same

Abstract: A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.

Display with current controlled light-emitting device

Abstract: A display includes an electric current controlled light-emitting device that emits light with a luminance depending on an electric current flowing therethrough. The display also includes a transistor that has a gate electrode, a source electrode, and a drain electrode, and controls the electric current based on a data voltage between one of the source and drain electrodes and the gate electrode; and a controller that controls a gate-to-source voltage and a gate-to-drain voltage of the transistor based on a change in the luminance of the electric current controlled light-emitting device while maintaining the transistor element in a saturation region.

Drain extended MOS transistor with improved breakdown robustness

Abstract: A drain-extended metal-oxide-semiconductor transistor ( 40 ) with improved robustness in breakdown characteristics is disclosed. Field oxide isolation structures ( 29 c ) are disposed between the source region ( 30 ) and drain contact regions ( 32 a , 32 b , 32 c ) to break the channel region of the transistor into parallel sections. The gate electrode ( 35 ) extends over the multiple channel regions, and the underlying well ( 26 ) and thus the drift region (DFT) of the transistor extends along the full channel width. Channel stop doped regions ( 33 ) underlie the field oxide isolation structures ( 29 c ), and provide conductive paths for carriers during breakdown. Parasitic bipolar conduction, and damage due to that conduction, is therefore avoided.

Forming a retrograde well in a transistor to enhance performance of the transistor

Abstract: A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

Threshold voltage compensation method for electroluminescent display devices

Abstract: An active matrix electroluminescent display device has a shorting transistor (30) connected between the gate and drain of the drive transistor (22). Means (42) is provided for measuring a voltage on the data line (6). The shorting transistor (30) can be used to discharge the voltage on the gate of the drive transistor (22) until it switches off. By storing the resultant voltage on the data line (6) through an address transistor (16), the data line is used as one of the control/measurement lines for the threshold measurement.

Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions

Abstract: The present invention relates to a Tunnel Field Effect Transistor (TFET), which utilizes angle implantation and amorphization to form asymmetric source and drain regions. The TFET further comprises a silicon germanium alloy epitaxial source region with a conductivity opposite that of the drain.

Method and apparatus providing CMOS imager device pixel with transistor having lower threshold voltage than other imager device transistors

Abstract: A transistor of a pixel cell for use in a CMOS imager with a low threshold voltage of about 0.3 V to less than about 0.7 V is disclosed. The transistor is provided with high dosage source and drain regions around the gate electrode and with the halo implanted regions and/or the lightly doped LDD regions and/or the enhancement implanted regions omitted from at least one side of the gate electrode. The low threshold transistor is electrically connected to a high voltage transistor with a high threshold voltage of about 0.7 V.

Ambipolar injection in a submicron-channel light-emitting tetracene transistor with distinct source and drain contacts

Abstract: We report on organic light-emitting transistors with a submicron-channel length, gold source, and calcium drain contacts. The respective contact metals allow efficient injection of holes and electrons in the tetracene channel material. Transistor characteristics were measured in parallel with electroluminescence being recorded by a digital camera focused on the transistor channel. In the case of submicron-channel lengths, the transistor source-drain current at higher gate voltages was determined by the source-drain voltage. At larger channel lengths, the source-drain current was limited by the injection of electrons from the calcium contact, as hole ejection to this contact was fully blocked. The hole blocking is explained in terms of a chemical reaction occurring at the Ca/tetracene interface.

Asymetric layout structures for transistors and methods of fabricating the same

Abstract: High power transistors are provided. The transistors include a source region (20) , a drain region (22) and a gate contact (24) . The gate contact is positioned between the source region and the drain region. First and second ohmic contacts are provided on the source and drain regions, respectively. The first and second ohmic contacts respectively define a source contact and a drain contact. The source contact and the drain contact have respective first and second widths. The first and second widths are different. Related methods of fabricating transistors are also provided.

Lighting control circuit for vehicle lamps

Abstract: The supply of a predetermined current to LEDs is controlled by using series regulators. In accordance with the controlled states of the series regulators, a switching regulator adjusts an output voltage relative to the LEDs to the maximum voltage. When a ground fault occurs at the anode of one of the LEDs, and when a short circuit occurs at the output terminal of the switching regulator and the output voltage drops abnormally, the operation of the switching regulator is halted. When the gate voltage of an NMOS transistor is raised due to the disconnection of one of the LEDs, or when the drain voltage of the transistor is raised due to a short circuit at one of the LEDs, a Zener diode becomes conductive and an NPN transistor and a PNP transistor are rendered on. Then, a current flows through a diode, and as the gate voltage has been lowered, the operation of the NMOS transistor is halted, so that the remaining, normal LEDs are protected when an abnormality occurs.

Method for manufacturing a cell transistor of a semiconductor memory device

Abstract: Disclosed is a method for manufacturing a cell transistor of a semiconductor memory device. The method comprises the steps of: forming device isolation films and a well on a semiconductor substrate; forming a threshold voltage adjust region by ion-implanting a first conductive impurity dopant into the well of the semiconductor substrate; performing a first thermal annealing on the semiconductor substrate where the threshold voltage adjust region is formed; forming a gate insulating film and gate electrodes on top of the semiconductor substrate between the device isolation films; forming a halo ion implantation region by ion-implanting a first conductive impurity dopant into the semiconductor substrate corresponding to a drain region exposed by the gate electrodes; performing a second thermal annealing on the semiconductor substrate where the halo ion implantation region is formed; and forming source/drain regions by ion-implanting a second conductive impurity dopant into the semiconductor substrate exposed by the gate electrodes. This method can reduce the turn-off leakage current of the cell transistor since the dopant dose of the threshold voltage adjust region can be reduced while maintaining the threshold voltage by increasing the dopant diffusion of the threshold voltage adjust region.

Transistor with dopant-bearing metal in source and drain

Abstract: A transistor and method of manufacturing thereof. A gate dielectric and gate are formed over a workpiece, and the source and drain regions of a transistor are recessed. The recesses are filled with a dopant-bearing metal, and a low-temperature anneal process is used to form doped regions within the workpiece adjacent the dopant-bearing metal regions. A transistor having a small effective oxide thickness and a well-controlled junction depth is formed.

Multi-state memory cell with asymmetric charge trapping

Abstract: A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide-nitride-oxide structure. An asymmetrical bias on the drain/source areas causes the drain/source area with the higher voltage to inject an asymmetric distribution hole by gate induced drain leakage injection into the trapping layer substantially adjacent that drain/source area.

Threshold Voltage Model for Deep-Submicrometer MOSFET's

Abstract: Based on analysis on short-channel effect and drain induced barrier lowering (DIBL) effect, a threshold voltage model for high-k MOSFET's is etablished by introducing a coefficient that interrelates the two effects. Influences of various factors on threshold voltage shift are simulated and investigated, and the optimal range of k values is obtained.

High performance fet with laterally thin extension

Abstract: A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs have a device channel and a gate above the device channel with a doped source/drain extension at said each end of the thin channel. A portion of a low resistance material layer (e.g., a silicide layer) is disposed on source/drain extensions. The portions on the doped extensions laterally form a direct contact with the doped source/drain extension. Any low resistance material layer on the gate is separated from the low resistance material portions on the source/drain extensions.

LDMOS transistor with enhanced termination region for high breakdown voltage with on-resistance

Abstract: A structure for making a LDMOS transistor ( 100 ) includes an interdigitated source finger ( 26 ) and a drain finger ( 21 ) on a substrate ( 15 ). Termination regions ( 35, 37 ) are formed at the tips of the source finger and drain finger. A drain ( 45 ) of a second conductivity type is formed in the substrate of a first conductivity type. A field reduction region ( 7 ) of a second conductivity type is formed in the drain and is wrapped around the termination regions for controlling the depletion at the tip and providing higher voltage breakdown of the transistor.

Quantum short-channel compact model for the threshold voltage in double-gate MOSFETs with high-permittivitty gate dielectrics

Abstract: An analytical model of the threshold voltage for long channel double-gate metal-oxide-semiconductor field effect transistor is developed, applicable to both symmetric and asymmetric structures with thin films ( 10). The model takes into account short-channel effects, carrier quantization and fringing-field induced barrier lowering induced by the high-permittivity gate layer. The model assumes a parabolic dependence of the potential with position in the silicon film at threshold, enabling the development of an analytical expression for the surface potential. Compared to previous models only derived for undoped films, the present approach considers both mobile charge and depleted charge terms in Poisson’s equation. The model is fully validated by numerical simulation and is used to predict the impact of the fringing-induced barrier lowering on the threshold voltage of double-gate devices as a function of the gate stack composition and the device gate length.

Shielded channel double-gate MOSFET: a novel device for reliable nanoscale CMOS applications

Abstract: In this paper, the unique features exhibited by a novel double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) in which the front gate consists of two side gates to 1) electrically shield the channel region from any drain voltage variation and 2) act as an extremely shallow virtual extension to the source/drain are presented. This structure exhibits significantly reduced short-channel effects (SCEs) when compared with the conventional DG MOSFET. Using two-dimensional (2-D) and two-carrier device simulation, the improvement in device performance focusing on threshold voltage dependence on channel length, electric field in the channel, subthreshold swing, and hot carrier effects, all of which can affect the reliability of complementary metal oxide semiconductor (CMOS) devices, was investigated.

Accumulation device with charge balance structure and method of forming the same

Abstract: An accumulation-mode field effect transistor includes a plurality of gates and a semiconductor region having a channel region adjacent to but insulated from each of the plurality of gates. The semiconductor region further includes a conduction region wherein the channel regions and the conduction region are of a first conductivity type. The transistor further includes a drain terminal and a source terminal configured so that when the accumulation-mode field effect transistor is in the on state a current flows from the drain terminal to the source terminal through the conduction region and the channel regions. A number of charge balancing structures are integrated with the semiconductor region so as to extend parallel to the current flow. In a blocking state, the charge balancing structures influence an electric field in the conduction region so as to increase the blocking capability of the accumulation-mode field effect transistor.

Body-tied triple-gate NMOSFET fabrication using bulk Si wafer

Abstract: We fabricated firstly body-tied triple-gate NMOSFETs that have fin top width of 30 nm, fin bottom width of 61 nm, fin height of 99 nm, and gate length of 116 nm. Fabrication process steps of the devices are compatible with that of conventional bulk planar channel MOSFET technology and explained in detail in this paper. This MOSFET shows excellent transistor characteristics, such as very low subthreshold swing, Drain Induced Barrier Lowering (DIBL) of 24 mV/V, almost no body bias effect, and orders of magnitude lower I SUB / I D than planar channel DRAM cell transistors. By optimizing process further, it is expected that cost effective body-tied triple-gate MOSFETs can be applied to real Integrated Circuits (ICs).

Field effect transistor with buried gate pattern

Abstract: A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate pattern and the tunneling insulating film extend into the source and drain regions. Thus, the field effect transistor efficiently stores charge carriers in the buried gate pattern and the floating channel region.

Vertical tunneling nano-wire transistor

Abstract: A vertical nano-wire transistor is formed on a substrate out of a vertical pillar having active regions of opposing conductivity in opposite ends of the pillar. In one embodiment, the source region is a p+ region in the substrate under the pillar and the drain region is an n+ region at the top of the pillar. A surround gate is formed around the pillar. The transistor operates by electron tunneling from the source valence band to the gate biasing induced n-type channels along the sidewalls of the pillar to the drain region, thus resulting in a drain current.

Electronic circuit, driving method thereof, electro-optical device, and electronic apparatus

Abstract: To reduce a time for applying a target voltage to a gate of a driving transistor. During an initializing period, both ends of a capacitive element become a short-circuited state by turning on transistors, so that node A and B becomes a voltage made by subtracting the threshold voltage Vthp of the driving transistor from a power source voltage VEL. During a writing period, the transistor is turned on and a data signal X-j is supplied to change the voltage at the node B as much as a voltage corresponding the current which is to flow into an OLED element. The node A is changed from the threshold voltage as much as the value obtained by dividing the voltage change by capacity ratio. During a light-emitting period, the transistor is turned on, so that the current corresponding to the voltage at the node A flows through the OLED element.