Showing papers on "Electronic packaging published in 2021"

Flexible thermal interface based on self-assembled boron arsenide for high-performance thermal management

Abstract: Thermal management is the most critical technology challenge for modern electronics. Recent key materials innovation focuses on developing advanced thermal interface of electronic packaging for achieving efficient heat dissipation. Here, for the first time we report a record-high performance thermal interface beyond the current state of the art, based on self-assembled manufacturing of cubic boron arsenide (s-BAs). The s-BAs exhibits highly desirable characteristics of high thermal conductivity up to 21 W/m·K and excellent elastic compliance similar to that of soft biological tissues down to 100 kPa through the rational design of BAs microcrystals in polymer composite. In addition, the s-BAs demonstrates high flexibility and preserves the high conductivity over at least 500 bending cycles, opening up new application opportunities for flexible thermal cooling. Moreover, we demonstrated device integration with power LEDs and measured a superior cooling performance of s-BAs beyond the current state of the art, by up to 45 °C reduction in the hot spot temperature. Together, this study demonstrates scalable manufacturing of a new generation of energy-efficient and flexible thermal interface that holds great promise for advanced thermal management of future integrated circuits and emerging applications such as wearable electronics and soft robotics.

Applications and Impacts of Nanoscale Thermal Transport in Electronics Packaging

Abstract: This review introduces relevant nanoscale thermal transport processes that impact thermal abatement in power electronics applications. Specifically, we highlight the importance of nanoscale thermal transport mechanisms at each layer in material hierarchies that make up modern electronic devices. This includes those mechanisms that impact thermal transport through: (1) substrates, (2) interfaces and two-dimensional materials, and (3) heat spreading materials. For each material layer, we provide examples of recent works that (1) demonstrate improvements in thermal performance and/or (2) improve our understanding of the relevance of nanoscale thermal transport across material junctions. We end our discussion by highlighting several additional applications that have benefited from a consideration of nanoscale thermal transport phenomena, including radio frequency (RF) electronics and neuromorphic computing. [DOI: 10.1115/1.4049293]

Combining Alumina Particles with Three-Dimensional Alumina Foam for High Thermally Conductive Epoxy Composites

Abstract: Ceramic/polymer composite with a high thermal conductivity is a candidate of insulating materials for electronic packaging. However, traditional polymer composites filled with alumina (Al2O3) powde...

Recent Advances in Thermal Metamaterials and Their Future Applications for Electronics Packaging

Abstract: Thermal metamaterials exhibit thermal properties that do not exist in nature but can be rationally designed to offer unique capabilities of controlling heat transfer. Recent advances have demonstrated successful manipulation of conductive heat transfer and led to novel heat guiding structures such as thermal cloaks, concentrators, etc. These advances imply new opportunities to guide heat transfer in complex systems and new packaging approaches as related to thermal management of electronics. Such aspects are important, as trends of electronics packaging toward higher power, higher density, and 2.5D/3D integration are making thermal management even more challenging. While conventional cooling solutions based on large thermal-conductivity materials as well as heat pipes and heat exchangers may dissipate the heat from a source to a sink in a uniform manner, thermal metamaterials could help dissipate the heat in a deterministic manner and avoid thermal crosstalk and local hot spots. This paper reviews recent advances of thermal metamaterials that are potentially relevant to electronics packaging. While providing an overview of the state-of-the-art and critical 2.5D/3D-integrated packaging challenges, this paper also discusses the implications of thermal metamaterials for the future of electronic packaging thermal management. Thermal metamaterials could provide a solution to nontrivial thermal management challenges. Future research will need to take on the new challenges in implementing the thermal metamaterial designs in high-performance heterogeneous packages to continue to advance the state-of-the-art in electronics packaging.

Stitching Graphene Sheets with Graphitic Carbon Nitride: Constructing a Highly Thermally Conductive rGO/g-C3N4 Film with Excellent Heating Capability.

Abstract: Driven by the evolution of electronic packaging technology for high-dense integration of high-power, high-frequency, and multi-function devices in modern electronics, thermal management materials h...

Enhancing the electrical insulation of highly thermally conductive carbon fiber powders by SiC ceramic coating for efficient thermal interface materials

Abstract: Mesophase pitch-based carbon fibers (MPCFs), which have ultrahigh intrinsic thermal conductivity and one-dimensional morphology with high-aspect ratios, can act as excellent fillers for improving the oriented heat dissipation rate of thermal interface materials (TIMs). However, the high electrical conductivity hinders their application in some electronic packaging fields. Herein, a SiC ceramic layer is uniformly and firmly coated on the surface of the powder-like MPCFs by a dynamic chemical vapor deposition method to obtain the high thermal conductivity and suitable electrical insulation. The ceramic coating layer exhibits a porous structure, complete encapsulation and adjustable thickness in the range of 90–600 nm. Employed as the thermal conductive fillers, the SiC-coated MPCF-derived TIMs exhibit comparable thermal conductivity and significantly enhanced electrical insulation performance compared with that from original carbon fiber. For instance, the pad prepared from the coated carbon fiber with a medium coating thickness of 200 nm shows a high through-plane thermal conductivity of 12.8 W m−1 K−1, high electrical resistivity of 3.4 × 1010 Ω cm and satisfactory breakdown voltage value of 1100 V mm−1. This work opens a new avenue to integrate the thermal conductivity and electrical insulation of carbon materials as thermal conductive fillers for electronic packaging.

Recent Advances on Thermally Conductive Adhesive in Electronic Packaging: A Review.

Abstract: The application of epoxy adhesive is widespread in electronic packaging. Epoxy adhesives can be integrated with various types of nanoparticles for enhancing thermal conductivity. The joints with thermally conductive adhesive (TCA) are preferred for research and advances in thermal management. Many studies have been conducted to increase the thermal conductivity of epoxy-based TCAs by conductive fillers. This paper reviews and summarizes recent advances of these available fillers in TCAs that contribute to electronic packaging. It also covers the challenges of using the filler as a nano-composite. Moreover, the review reveals a broad scope for future research, particularly on thermal management by nanoparticles and improving bonding strength in electronic packaging.

An Overview of AI-Assisted Design-on-Simulation Technology for Reliability Life Prediction of Advanced Packaging.

Abstract: Several design parameters affect the reliability of wafer-level type advanced packaging, such as upper and lower pad sizes, solder volume, buffer layer thickness, and chip thickness, etc. Conventionally, the accelerated thermal cycling test (ATCT) is used to evaluate the reliability life of electronic packaging; however, optimizing the design parameters through ATCT is time-consuming and expensive, reducing the number of experiments becomes a critical issue. In recent years, many researchers have adopted the finite-element-based design-on-simulation (DoS) technology for the reliability assessment of electronic packaging. DoS technology can effectively shorten the design cycle, reduce costs, and effectively optimize the packaging structure. However, the simulation analysis results are highly dependent on the individual researcher and are usually inconsistent between them. Artificial intelligence (AI) can help researchers avoid the shortcomings of the human factor. This study demonstrates AI-assisted DoS technology by combining artificial intelligence and simulation technologies to predict wafer level package (WLP) reliability. In order to ensure reliability prediction accuracy, the simulation procedure was validated by several experiments prior to creating a large AI training database. This research studies several machine learning models, including artificial neural network (ANN), recurrent neural network (RNN), support vector regression (SVR), kernel ridge regression (KRR), K-nearest neighbor (KNN), and random forest (RF). These models are evaluated in this study based on prediction accuracy and CPU time consumption.

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

Abstract: With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging.

Fabrication Process for On-Board Geometries Using a Polymer Composite-Based Selective Metallization for Next-Generation Electronics Packaging

Abstract: Advancements in production techniques in PCB manufacturing industries are still required as compared to silicon-ICs fabrications. One of the concerned areas in PCBs fabrication is the use of conventional methodologies for metallization. Most of the manufacturers are still using the traditional Copper (Cu) laminates on the base substrate and patterning the structures using lithography processes. As a result, significant amounts of metallic parts are etched away during any mass production process, causing unnecessary disposables leading to pollution. In this work, a new approach for Cu metallization is demonstrated with considerable step-reducing pattern-transfer mechanism. In the fabrication steps, a seed layer of covalent bonded metallization (CBM) chemistry on top of a dielectric epoxy resin is polymerized using actinic radiation intensity of a 375 nm UV laser source. The proposed method is capable of patterning any desirable geometries using the above-mentioned surface modification followed by metallization. To metallize the patterns, a proprietary electroless bath has been used. The metallic layer grows only on the selective polymer-activated locations and thus is called selective metallization. The highlight of this production technique is its occurrence at a low temperature (20–45 °C). In this paper, FR-4 as a base substrate and polyurethane (PU) as epoxy resin were used to achieve various geometries, useful in electronics packaging. In addition, analysis of the process parameters and some challenges witnessed during the process development are also outlined. As a use case, a planar inductor is fabricated to demonstrate the application of the proposed technique.

Thermal analysis of electronic packaging structure using isogeometric boundary element method

Abstract: The purpose of this paper is to carry out heat transfer analysis of integrated circuit (IC) packaging structures by the isogemoetric boundary element method (IGABEM). In service time, chips of electronic packaging structure produce lots of heat, which leads to resultant equations including domain integrals. In this work, the radial integration method is used to deal with domain integrals caused by the heat source. Since material properties of electronic packaging structure are piecewise continuous, the subregion isogemoetric boundary element method is introduced in the present IGABEM. In addition, the multi-scale property of structure leads to challenge of IGABEM analysis in electronic packaging problems. This largely results from the difficulty of integrating nearly singular integrals in an accurate and efficient manner. To deal with this problem, a hybrid nearly singular integration scheme, which delivers results of engineering accuracy in an optimal time is used in this work. Finally, a set of numerical examples demonstrate the ability of the present IGABEM to produce accurate temperature distributions.

Board Level Temperature Cycling Reliability of mmWave Modules on Hybrid Substrates

Abstract: The field of consumer and automotive electronics is becoming increasingly important for applications of mmWave technology. Innovative approaches and materials for electronics packaging are currently being developed. The focus on improving the performance and the reliability induces an increased demand for in-depth analysis and testing. In this study, the thermo-mechanical behaviour of mmWave modules mounted onto a standard or a hybrid substrate is investigated. A board level reliability study is performed according to the automotive standard AEC-Q100 grade 1 specification. Findings after temperature cycling test at −55°C to + 150°C will be presented. Commercially available FR4 substrate materials with high- and suitable low transmission loss characteristics are selected to meet both automotive and high frequency requirements. The mmWave module is made of one low loss material. The impact of two substrate configurations on the board level reliability of the mmWave module is investigated. Considering the different material properties and the large package dimension, temperature changes will cause severe stress to the board level solder interconnects (alloy SAC305, diameter). The performance of the mmWave test vehicle in terms of the solder joint damage behaviour under temperature cycling testing will be analysed in this study. Both specimen configurations successfully passed electrical tests after up to 1,000 cycles temperature cycling. Cross sections and electrical analysis show a better performance of the hybrid configuration at high cycle counts.

Voids Inspection Capability Study in First-Level Interconnects for Flip Chip Packages

Abstract: The evolution of electronic packaging to enable 3D heterogeneous integration has led to a continuous downscaling of solder interconnects. With the emergence of packaging technologies such as silicon bridges, interposers and die-to-die stacking, micro bumps in electronic packages are getting smaller and smaller. The shrinkage of bump size to cater for higher I/Os in increasingly complex packaging design can lead to weaker interconnect joints. Common defects that have plagued bigger solder joints could become critical in smaller micro bumps. One such defect is voiding. The presence of voids in small micro bumps not only reduces solder volume and affects joint structural integrity but also restricts current flow and increases current density in the joint. This paper presents the study of void formation in first-level interconnects and the inspection capability of void detection.

Humidity Control in Electronic Devices: Water Sorption Properties of Desiccants and Related Humidity Build-Up in Enclosures

Abstract: A common concern with electronics packaging is the reduction of moisture ingress into the devices. One option to consider is the use of water absorption desiccant. Its criteria for selection should be its water capacity property, while its regeneration temperature has to be taken into account. Electronic devices are exposed to all kinds of harsh cyclic environments, and assuring a low level of humidity inside the devices implies the replacement of the desiccant once its saturation content is reached. This may not be applicable, or the frequency of replacement may represent a high cost. Using the dissipated heat from the electronic devices during the “ON” time may be a low-cost process for the regeneration of the desiccant, therefore increasing its lifetime. This article presents the experimental investigation of the performance of different desiccants on water absorption and regeneration. Analysis and test results show that the desiccant system continuously maintains a lower humidity inside the electronic enclosures over the tested time of cyclic exposure if they can be regenerated using device self-heating.

Toward high-thermal-conductivity polymers

Abstract: Polymers have been extensively used as encapsulating materials in electronic packaging, but low thermal conductivity creates an obstacle for effective heat dissipation. To mitigate this, one fundamental route is to develop high-thermal-conductivity (high-κ) polymers. Recently in Science Advances, Li and colleagues9 proposed a polymer film created by solution-gel-shearing ultrahigh-molecular-weight polyethylene, possessing both high thermal conductivity and electrical insulation properties simultaneously.

Comparative Reliability of Inkjet-Printed Electronics Packaging

Abstract: This article compares the thermomechanical behavior of 3-D inkjet-printed microelectronics devices relative to those fabricated from traditional methods. It discusses the benefits and challenges in the adoption of additive manufacturing methods for microelectronics manufacture relative to conventional approaches. The critical issues related to the design and reliability of additively manufactured parts and systems stem from the change in the manufacturing process and the change in materials utilized. This study uses numerical modeling techniques to gain insight into these issues. This article is an extension of the same topic presented at the 2018 IEEE Electronics Packaging Technology Conference. An introduction providing an overview of the area, covering salient academic research activities and discussing progress toward commercialization is presented. The state-of-the-art modular microelectronics fabrication system developed within the EU NextFactory project is introduced. This system has been used to manufacture several test samples, which were assessed both experimentally and numerically. A full series of JEDEC tests showed that the samples were reliable, successfully passing all tests. The numerical model assessing the mechanical behavior of an inkjet-printed structure during layer-by-layer fabrication is presented. This analysis predicts that the stresses induced by the UV cure process are concentrated toward the extremities of the part and, in particular, in the lower layers which are constrained by the print platform. Subsequently, a model of a multilayer microelectronics structure undergoing JEDEC thermal cycling is presented. The model assesses the differences in mechanical properties between a conventional FR4/copper structure and an inkjet-printed acrylic/silver structure. The model identified that the influence of the sintering process on subsequent material properties, behavior of the inject-printed structure, and reliability of the inject-printed structure is significant. Key findings are that while stresses in the conventional and inkjet boards are relatively similar, the inkjet-printed board exhibits significantly greater deformation than the standard board. Furthermore, the mechanical stresses in the inkjet fabricated board are strongly dependent on the elastic modulus of the sintered silver material, which, in turn, is dependent on the sintering process.

Laminar Metal Foam: A Soft and Highly Thermally Conductive Thermal Interface Material with a Reliable Joint for Semiconductor Packaging.

Abstract: Future electronic packaging technology requires semiconductor chips having a larger size and higher power for advanced applications, e.g., new energy conversion systems, electric vehicles, and data center servers, yet traditional thermal interface materials (TIMs) with a high thermal conductivity are generally stiff materials with weak joints, which cause the accumulated thermal stress to concentrate at the chip corners, leading to cracking and popcorn problems. To address such a critical challenge, herein for the first time we report a low-cost and high-performance porous copper (Cu)-indium (In) laminar structure as TIM, which can provide a superior thermal conductivity (50 W m-1 K-1) comparable to indium, yet the Young's modulus (1.0 GPa) is an order of magnitude lower than indium, which is a state-of-the-art value. Additionally, the In-based intermetallic compound (IMC) joints enable more robust mechanical interconnection above the melting point of pure indium, providing better high-temperature performance. The discontinuous IMCs spread the global interfacial thermal stress into numerous isolated local areas, ensuring a reliable joint to resist thermal-mechanical fatigue. In the silicon-TIM-copper package testing vehicles with a large die size (1 × 1 square inch), this structure shows excellent thermal management ability and superior reliability, compared with classical indium and classic commercial silver pastes.

Emerging Interconnection Technology and Pb-Free Solder Materials for Advanced Microelectronic Packaging

Abstract: In the field of electronics packaging, Pb-bearing solder alloys are mostly used as robust interconnecting materials [...]

Sinterconnects: All-Copper Top-Side Interconnects Based on Copper Sinter Paste for Power Module Packaging

Abstract: Copper sinter paste has been recently established as a robust die-attach material for high -power electronic packaging. This paper proposes and studies the implementation of copper sinter paste materials to create top-side interconnects, which can substitute wire bonds in power packages. Here, copper sinter paste was exploited as a fully printed interconnect and, additionally, as a copper clip-attach. The electrical and thermal performances of the copper-sinter paste interconnections (“sinterconnects”) were compared to a system with wire bonds. The results indicate comparable characteristics of the sinterconnect structures to the wire-bonded ones. Moreover, the performance of copper sinterconnects in a power module was further quantified at higher load currents via finite element analysis. It was identified that the full-area thermal and electrical contact facilitated by the planar sinterconnects can reduce ohmic losses and enhance the thermal management of the power packages.

An ultra-thin and highly flexible multilayer Printed Circuit Board based on Parylene

Abstract: Following the current trends towards Industry 4.0 and the Internet of Things, flexible electronics and sensors are a key enabling technology for the realization of wearables and geometry adaptive devices. Within this study, we present a new approach for the fabrication of an ultra-thin and highly flexible printed circuit board (PCB), featuring multiple metallization layers and a thickness of < 20 μm only. Doing so, the polymer Parylene served as substrate material, as dielectric between the metallization layers as well as for the encapsulation and protection. Within this paper, the concept of this new approach as well as different options for the fabrication technologies and possible applications are presented in detail. Finally, the fabricated Parylene based ultra-thin flexible PCB was characterized mechanically and electrically.

Laser-Assisted Sintering of Silver Nanoparticle Paste for Bonding of Silicon to DBC for High-Temperature Electronics Packaging

Abstract: This article presents the development of a laser-assisted sintering method of a silver nanoparticle paste for bonding of a silicon chip to a direct bonded copper (DBC) substrate for high-temperature electronics packaging applications. The effects of the bonding parameters such as laser power, bonding pressure, and time on shear strength were studied. For comparison, samples using hotplate bonding were also produced and studied. Shear strength, cross section, and fracture surface analysis were carried out in reliability studies. The results show that shear strength of 10 MPa can be achieved at the bonding pressure of 3 MPa, laser power of 70 W, and a very short irradiation time of 1 min. The shear strength reached 20 MPa when the irradiation time was increased to 5 min. The research indicates that the shear strength can be improved by increasing the bonding pressure, laser power, and hence the sintering temperature and the irradiation time. The laser-assisted method with a short irradiation time of 5 min can produce the same level of shear strength as compared with the hotplate-based approach requiring a sintering time of tens of minutes. With the ability of fast and localized heating effect, the laser-assisted sintering method can improve the manufacturing efficiency for packaging of high-temperature electronics and sensors.