Showing papers on "Etching (microfabrication) published in 1994"

VLSI fabrication principles : silicon and gallium arsenide

Abstract: Material Properties. Phase Diagrams and Solid Solubility. Crystal Growth and Doping. Diffusion. Epitaxy. Ion Implantation. Native Films. Deposited Films. Etching and Cleaning. Lithographic Processes. Device and Circuit Fabrication. Appendix. Index.

Fabrication of si nanostructures with an atomic force microscope

Abstract: A method for fabricating Si nanostructures with an air‐operated atomic force microscope (AFM) is presented. An electrically conducting AFM tip is used to oxidize regions of size 10–30 nm of a H‐passivated Si (100) surface at write speeds up to 1 mm/s. This oxide serves as an effective mask for pattern transfer into the substrate by selective liquid etching. The initial oxide growth rate depends exponentially on the applied voltage which produces an effective ‘‘tip sharpening’’ that allows small features to be produced by a relatively large diameter tip.

Method of etching an oxide layer

Abstract: A method of etching an oxide layer is disclosed. First, a resist layer is formed on an oxide layer on a substrate. Next, a photosensitive layer is formed on the oxide layer and patterned to expose regions of the oxide layer to be removed. The exposed regions may overlie a nitride layer, and may overlie a structure such as a polysilicon gate. The etch is performed such that polymer deposits on the photosensitive layer, thus eliminating interactions between the photosensitive layer and the plasma. In this way, a simple etch process allows for good control of the etch, resulting in reduced aspect ratio dependent etch effects, high oxide:nitride selectivity, and good wall angle profile control.

Two‐dimensional modeling of high plasma density inductively coupled sources for materials processing

Abstract: Inductively coupled plasma sources are being developed to address the need for high plasma density (1011–1012 cm−3), low pressure (a few to 10–20 mTorr) etching of semiconductor materials. One such device uses a flat spiral coil of rectangular cross section to generate radio‐frequency (rf) electric fields in a cylindrical plasma chamber, and capacitive rf biasing on the substrate to independently control ion energies incident on the wafer. To investigate these devices we have developed a two‐dimensional hybrid model consisting of electromagnetic, electron Monte Carlo, and hydrodynamic modules; and an off line plasma chemistry Monte Carlo simulation. The results from the model for plasma densities, plasma potentials, and ion fluxes for Ar, O2, Ar/CF4/O2 gas mixtures will be presented.

SCREAM I: A single mask, single-crystal silicon, reactive ion etching process for microelectromechanical structures

Abstract: A single-crystal slhcon, high aspect ratlo, low-temperature process sequence for the fabrlcatlon of suspended rmcroelectromechamcal structures (MEMS) usmg a smgle hthography step and reactwe Ion etching (RIE) IS presented The process IS called SCRJZAM I (single-crystal reactwe etchmg and metalhzatmn) SCREAM I IS a bulk mlcromachmmg process that uses RIE of a s~hcon substrate to fabricate suspended movable smgle-crystal s&on (SCS) beam structures Beam elements wth aspect ratios of 10 to 1 and widths rangmg from 0 5 to 4 0 Frn have been fabricated All process steps are low temperature (<3OO “C), and only conventronal sd~con fabrlcation tools are used photohthography, RIE, MIE, plasma-enhanced chemxal-vapor deposrtlon (PECVD) and sputter deposlhon SCREAM I IS a self-ahgned process and uses a smgle lithography step to define beams and structures srmultaneously as well as all necessary contact pads, electrIcal mterconnects and lateral capaators SCREAM I has been specifically deslgned for integration with standard Integrated cmxnt (IC) processes, so MEM deuces can be fabricated adjacent to prefabricated analog and dIgItal carcuitry In this paper we present process parameters for the fabncatlon of discrete SCREAM I devices We also discuss mask design rules and show micrographs of fabncated deuces

PCR in a silicon microstructure.

Abstract: Devices for performing polymerase chain reactions (PCR) have been developed for use with photolithographed silicon. Microchambers capable of holding between 5.0 and 10 microL of PCR reagents were constructed by etching specific areas of rectangular silicon chips (17 x 15 mm), which were then capped with Pyrex glass. These silicon devices (PCRChips), which were etched to depths of 40-80 microns, permitted free flow of fluids in the microchannels and microchambers. Access to the microchambers was through holes in the silicon. Thermal cycling of the PCR reagents was achieved by placing the disposable PCRChip in a small holder containing a computer-controlled Peltier heater-cooler. Successful amplification was demonstrated by electrophoresis of products in agarose gel containing ethidium bromide, and the migration of the product was compared with that obtained in a commercially available thermal cycler. The thermal characteristics of the silicon, coupled with the high surface area to volume ratio in the new devices, are particularly advantageous features for amplification by PCR.

Self‐limiting oxidation for fabricating sub‐5 nm silicon nanowires

Abstract: The ability to control structural dimensions below 5 nm is essential for a systematic study of the optical and electrical properties of Si nanostructures. A combination of electron beam lithography, NF3 reactive ion etching, and dry thermal oxidation has been successfully implemented to yield 2‐nm‐wide Si nanowires with aspect ratio of more than 100 to 1. With a sideview transmission electron microscopy technique, the oxidation progression of Si nanowires was characterized over a range of temperature from 800 to 1200 °C. A previously reported self‐limiting oxidation phenomenon was found to occur only for oxidation temperatures below 950 °C. A preliminary model suggests that increase in the activation energy of oxidant diffusivity in a highly stressed oxide may be the main mechanism for slowing down the oxidation rate in the self‐limiting regime.

Micromachined silicon electrostatic chuck

Abstract: An electrostatic chuck is faced with a patterned silicon plate 11, createdy micromachining a silicon wafer, which is attached to a metallic base plate 13. Direct electrical contact between the chuck face 15 (patterned silicon plate's surface) and the silicon wafer 17 it is intended to hold is prevented by a pattern of flat-topped silicon dioxide islands 19 that protrude less than 5 micrometers from the otherwise flat surface of the chuck face 15. The islands 19 may be formed in any shape. Islands may be about 10 micrometers in diameter or width and spaced about 100 micrometers apart. One or more concentric rings formed around the periphery of the area between the chuck face 15 and wafer 17 contain a low-pressure helium thermal-contact gas used to assist heat removal during plasma etching of a silicon wafer held by the chuck. The islands 19 are tall enough and close enough together to prevent silicon-to-silicon electrical contact in the space between the islands, and the islands occupy only a small fraction of the total area of the chuck face 15, typically 0.5 to 5 percent. The pattern of the islands 19, together with at least one hole 12 bored through the silicon veneer into the base plate, will provide sufficient gas-flow space to allow the distribution of the helium thermal-contact gas.

Reactive ion etching of GaN using BCl3

Abstract: Reactive ion etching with SiCl4 and BCl3 of high quality GaN films grown by plasma enhanced molecular beam epitaxy is reported. Factors such as gas chemistry, flow rate, and microwave power affecting the etching rate are discussed. The etch rate has been found to be larger with BCl3 than with SiCl4 plasma. An etch rate of 8.5 A/s was obtained with the BCl3 plasma for a plasma power of 200 W, pressure of 10 mTorr, and flow rate of 40 sccm. Auger electron spectroscopy (AES) was used to investigate the surface of GaN films after etching. Oxygen contamination has been detected from the AES profiles of etched GaN samples.

Charge Damage Caused by Electron Shading Effect

Abstract: An antenna covered with photoresist patterns having high-aspect-ratio openings caused charge damage to the gate oxide in various processing plasmas. This damage increased with the pattern's aspect ratio, and occurred even when the test wafer was cut into chips about 5 mm square and mounted on a wafer with insulation. These results prove the electron shading model: the photoresist patterns shade the antenna from electrons of oblique incidence, resulting in local charging occurring without a wafer-scale voltage difference, which is essential for conventional charging. The damaging current from this mechanism increased by a factor of more than ten with a decrease in the gate oxide thickness only from 8 nm to 6 nm, implying that the degree of shading depends on the gate charging voltage. An improved model is proposed to accommodate this strong dependence.

Etching titanium nitride using carbon-fluoride and carbon-oxide gas

Abstract: A process for etching titanium nitride on a substrate 20 is described. In the process, a substrate 20 having a titanium nitride layer 24c thereon, and an insulative oxide layer 26 on the titanium nitride layer 24c is placed in a process chamber 42. Either a single stage, or a multiple stage version, of the process is then effected to etch the insulative oxide and titanium nitride layers. In the single stage version, the insulative oxide layer 26 and titanium nitride layer 24c are etched in a single stage, by introducing an etchant gas comprising carbon-fluoride gas and carbon-oxide gas into the process chamber 42, and generating a plasma from the etchant gas. The multiple stage version, comprises a first stage in which the insulative oxide layer 26 is etched using a plasma generated from carbon-fluoride gas, and a second stage in which the titanium nitride layer 24c is etched using a plasma generated from an etchant gas comprising carbon-fluoride gas and carbon-oxide gas. Suitable carbon-fluoride gases comprise CF 3 , CF 4 , CH 3 F, CHF 3 , C 2 F 6 , C 3 F 8 , C 4 F 8 or C 4 F 10 , and suitable carbon-oxide gases comprise CO or CO 2 .

Manufacture of semiconductor device

Abstract: PROBLEM TO BE SOLVED: To provide a method for highly selectively etching an underlying silicon oxide film in a semiconductor device, when processing a wiring layer and a silicon substrate at the same time. SOLUTION: When a wiring layer and a silicon substrate are processed at the same time, a flow rate of oxygen in a mixture gas such halogen gases as chlorine gas and an oxygen gas is set at 30-60%, with respect to the total gas low rate. A gas pressure in a reaction chamber 204 is first set at 1×10 torr or lower by a vacuum pump 211, and then a mixture gas containing an O2 gas and a Cl gas in a proportion of 25 sccm of O2 gas and 45 sccm of Cl gas are introduced separately through respective gas inlet pipes 210. Next, a magnetic field is made by an exciting coil, and about 1.75 kW microwave is guided from a microwave oscillator 203 into a plasma generation chamber 201 for generating a plasma of the mixture gas. Further, about 40 W of high-frequency power is applied form a high-frequency power source 208 to an electrode 206 for applying a bias electric field on a semiconductor substrate 207 fixed by an electrostatic attraction thereon for etching the substrate.

Nonlinear electrical transport in porous silicon.

Abstract: We present a study of the electrical transport in porous Si layers prepared by anodic etching of two different kinds of (100) p-type Si substrates. It is shown that by choosing a sufficiently thick layer, the problem of injection from the contacts can be eliminated. In this way we measure the intrinsic transport properties. The results suggest that a Poole-Frenkel type of mechanism accounts for the observed electric-field-enhanced conduction.

Optimization of dry etching through the control of helium backside pressure

Abstract: In a dry non-isotropic etching process, backside cooling by helium controls the rate and uniformity of etching in a thermal silicon layer, the taper of profiles etched into silicon dioxide layers, and the dimension and uniformity of etched structures in a polycide or polysilicon layer, on the surface of a silicon wafer. Helium pressures from greater than 2 torr to more than 10 torr are satisfactorily utilized to produce these effects.

A micromachined silicon sieve electrode for nerve regeneration applications

Abstract: A micromachined silicon sieve electrode has been developed and fabricated to record from and stimulate axons/fibers of the peripheral nervous system by utilizing the nerve regeneration principle. The electrode consists of a 15-/spl mu/m-thick silicon support rim, a 4-/spl mu/m-thick diaphragm containing different size holes to allow nerve regeneration, thin-film iridium recording/stimulating sites, and an integrated silicon ribbon cable, all fabricated using boron etch-step and silicon micromachining techniques. The thin diaphragm is patterned using reactive ion etching to obtain different size holes with diameters as small as 1 /spl mu/m and center-center spacings as small as 10 /spl mu/m. The holes are surrounded by 100-200 /spl mu/m/sup 2/ anodized iridium oxide sites, which can be used for both recording and stimulation. These sites have impedances of less than 100 k/spl Omega/ @ 1 kHz and charge delivery capacities in the 4-6 mC/cm/sup 2/ range. The fabrication process is single-sided, has high yield, requires only five masks, and is compatible with integrated multilead silicon ribbon cables. The electrodes were implanted between the cut ends of peripheral taste fibers of rats (glossopharyngeal nerve), and axons functionally regenerated through holes, responding to chemical, mechanical, and thermal stimuli. >

Fluorocarbon high‐density plasmas. I. Fluorocarbon film deposition and etching using CF4 and CHF3

Abstract: Fluorocarbon film deposition in discharges used for oxide etching plays a key role in determining the profile shape of contact holes and the etch selectivity with respect to the mask and the underlayer. For low‐density capacitatively coupled rf discharges this deposition is due to neutral radicals. We report a study of fluorocarbon film deposition and etching phenomena in electron cyclotron resonance (ECR) discharges of CF4 and CHF3. Plasma operation without rf sample bias in the pressure range below 10 mTorr results in the deposition of fluorocarbon films for both gases, with the highest deposition rate in each case at 2 mTorr (≂120 nm/min for a 1000 W CF4 plasma and ≂180 nm/min for CHF3 using the same conditions). For CF4 this behavior differs dramatically from that seen for conventional rf diode plasmas where no deposition occurs. The deposition is due to the more efficient breakdown and ionization of CF4 and CHF3 in the ECR discharge and the lack of energetic ion bombardment of the substrate as compar...

Porosity superlattices: a new class of Si heterostructures

Abstract: Porosity superlattices have been investigated by transmission electron microscopy, photoluminescence and reflectance spectroscopy. The superlattices were formed on p-type doped Si using two different techniques. Firstly, for homogeneously doped substrates we have periodically varied the formation current density and thereby the porosity. Secondly, the current density was kept constant while etching was performed on periodically doped Si layers. For the first type of superlattices the layer thicknesses were determined by transmission electron microscopy. The results are in good agreement with the values calculated from the etching rate and time. For both types of superlattices, reflectance and photoluminescence spectra show strong modulation due to the periodicity of the superlattice.

Method of forming a capacitor

Abstract: A method of forming a capacitor includes, a) providing a substrate; b) etching into the substrate to provide a depression in the substrate, the depression having a sidewall which is angled from vertical; c) providing a conformal layer of hemispherical grain polysilicon within the depression and over the angled sidewall, the layer of hemispherical grain polysilicon less than completely filling the depression; and d) ion implanting the hemispherical grain polysilicon layer with a conductivity enhancing impurity Preferred methods of providing the depression where the substrate comprises SiO 2 include a dry, plasma enhanced, anisotropic spacer etch utilizing reactant gases of CF 4 and CHF 3 provided to the substrate at a volumetric ratio of 1:1, and facet sputter etching

Improvement of grain size and deposition rate of microcrystalline silicon by use of very high frequency glow discharge

Abstract: The influence of the plasma excitation frequency on the growth conditions and the material properties of microcrystalline silicon prepared by plasma enhanced chemical vapor deposition at low deposition temperature is investigated. It is found that an increase of the plasma excitation frequency leads to a simultaneous increase of the growth rate, the grain size, and the Hall mobility of microcrystalline silicon. This is attributed to an effective selective etching of disordered material creating more space to develop crystalline grains, while also more species for faster growth of the crystallites are available.

Method for etching boron nitride

Abstract: The subject invention provides a method of enhancing the etch rate of boron nitride which comprises doping a layer of boron nitride with an element from Group IVA of the Periodic Table of the Elements, such as silicon, carbon, or germanium. The doped boron nitride layer can be wet etched at a faster rate with hot phosphoric acid than was possible prior to doping the boron nitride.

Method of micro-machining an integrated sensor on the surface of a silicon wafer

Abstract: A method for micromachining the surface of a silicon substrate which encompasses a minimal number of processing steps. The method involves a preferential etching process in which a chlorine plasma etch is capable of laterally etching an N+ buried layer beneath the surface of the bulk substrate. Such a method is particularly suitable for forming sensing devices which include a small micromachined element, such as a bridge, cantilevered beam, membrane, suspended mass or capacitive element, which is supported over a cavity formed in a bulk silicon substrate. The method also permits the formation of such sensing devices on the same substrate as their controlling integrated circuits. This invention also provides novel methods by which such structures can be improved, such as through optimizing the dimensional characteristics of the micromachined element or by encapsulating the micromachined element.

Process of fabricating a semiconductor substrate

Abstract: A process for preparing a semiconductor substrate comprises a step of porousifying a silicon monocrystalline substrate to form a porous layer, a step of making a silicon monocrystalline thin film to epitaxially grow on a surface of the porous layer, a step of oxidizing the surface of the epitaxial growth layer, a step of forming a deposited film on the oxidized surface, thereby obtainig a first substrate, a step of closely contacting the deposited film of the first substrate to a second substrate, a step of heat treating the closely contacted substrates and a step of selectively etching the porous layer.

Fluorocarbon high‐density plasmas. II. Silicon dioxide and silicon etching using CF4 and CHF3

Abstract: We report a study of the application of CF4 and CHF3 electron cyclotron resonance (ECR) discharges to selective etching of SiO2 over Si. Due to significant fluorocarbon film deposition for plasma operation without rf sample bias in the pressure range below 10 mTorr, rf biasing is required for etching of SiO2 and Si. The rf threshold voltage for etching is 55 V for CHF3 and 35 V for CF4 at a pressure of 1 mTorr. At 100 V rf bias, silicon dioxide etch rates were greater than ≂600 nm/min in CF4 and 450 nm/min for 1000 W plasmas at 1 mTorr pressure. A plot of the oxide etch rate vs rf bias exhibits a fluorocarbon film suppression regime at low rf voltages and an oxide sputtering regime at higher rf voltages. In the fluorocarbon suppression regime, the etch rate is primarily determined by fluorocarbon deposition which results in a thin fluorocarbon film being present on the SiO2 surface during steady‐state etching. In the oxide sputtering regime, the oxide etch rate increases linearly with the ion current to t...

Method for anisotropic plasma etching of substrates

Abstract: A method for anisotropic plasma etching of silicon substrates, a plasma etching apparatus for implementing the method, and an electronic device manufactured according to the method, which method includes the steps of positioning a substrate having a surface to be depleted by etching within a processing chamber and in communication with an electrode; introducing a gas mixture including an etching gas and a passivating gas which are essentially free of chlorine, bromine or iodine into the processing chamber, the etching gas including at least one halogen or halogen compound and the passivating gas including at least one polymer-generating monomer; exciting the gas mixture with electromagnetic radiation effective to produce a plasma containing ions; and applying a voltage to one of the substrate or the electrode to accelerate the ions toward the substrate and provide the ions with an energy ranging from about 1 to about 40 eV, preferably from about 10 to about 30 eV, when the ions impinge on the surface of the substrate.

Characteristics of chemically assisted ion beam etching of gallium nitride

Abstract: Chemically assisted ion beam etching (CAIBE) characteristics of gallium nitride (GaN) have been investigated using a 500‐eV Ar ion beam directed onto a sample in a Cl2 ambient. Enhanced etch rates were obtained for samples etched in the presence of Cl2 over those etched only by Ar ion milling at a substrate temperature of 20 °C. The CAIBE etch rates were further enhanced at higher substrate temperatures whereas etch rates for Ar ion milling were not influenced by substrate temperature. Etch rates as high as 210 nm/min are reported. The etch rates reported here are the highest so far reported for GaN. Anisotropic etch profiles and smooth etched surfaces in GaN have been achieved with CAIBE.

The Etching Mechanisms of SiO2 in Hydrofluoric Acid

Abstract: The different equilibria in and solutions are examined and the etching reaction of is investigated as a function of the different species present in the solution. A new model for the etching mechanism of is developed based on the existence of the dimer of , .

Method of manufacturing semiconductor device

Abstract: PURPOSE:To make an insulating film flat with high precision by a method wherein a film to be patterned which has an undercut and resist to be reversely patterned are formed on the insulating film and the resist on the insulating film and the insulating film are etched at the same time. CONSTITUTION:First and second resists 6, 8 are mutually reverse sensitivity and also when these resists 6, 8 are patterned, the identical exposing mask 7 is used with the identical position relationship. Therefore, the first resist 6 is used as a mask and is patterned, and the second resist 8 has reversed patterns with respect to that of the film to be patterned. Accordingly, when the second resist 8 and the insulating film 4 for filling steps are etched at the same time, an insulating film 4 is etched from a projecting part exposed from the second resist 8 and a recessed part coated with the second resist 8 is etched after the second resist 8 is completely removed by etching. Thus, the flatting of the insulating film 4 can be carried out with good controllability and high precision.

Dry etching for coherent refractive microlens arrays

Abstract: Coherent arrays of refractive micro-optics are fabricated in the surface of silicon using a combination of lithographic and reactive-ion etching (RIE) techniques. The aspheric profile can be approximated in a stepwise manner by iterative steps of photolithography and RIE (binary optics technology), by direct etching of a preshaped polymer microlens etch mask into the substrate, or by analog etching of a lens profile directly into the substrate through a pinhole mask.

Soi substrate fabrication

Abstract: A back-etch silicon-on-insulator SOI process that has a silicon handle wafer with an oxide layer bonded at room temperature to a silicon device wafer with an etch stop and silicon device layer. The surfaces that are bonded at room temperature are first conditioned to be hydrophilic. After bonding, the edges of the layers are sealed. The silicon device wafer, the etch-stop layer and the device layer are boron doped. Most of the silicon device wafer is ground away. Then, the remaining portion of the silicon device wafer and the etch stop layer are chemically etched away, thereby leaving a uniform layer of silicon device layer on the oxide layer of the silicon handle wafer. Because the bonding, grinding and selective etching are performed at room temperature, inter-diffusion of the boron between the various layers is prevented and thus permits the selective etching process to result in a nearly perfect silicon device layer in terms of an even-surfaced, defect-free and thin layer on the buried oxide layer of silicon handle wafer. The resulting SOI wafer is then annealed at a high temperature, prior to device processing.