Showing papers on "Frequency multiplier published in 2006"

A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications

Abstract: A 0.13-mum SiGe BiCMOS double-conversion superheterodyne receiver and transmitter chipset for data communications in the 60-GHz band is presented. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, IF amplifier strip, quadrature IF-to-baseband mixers, phase-locked loop (PLL), and frequency tripler. It achieves a 6-dB noise figure, -30 dBm IIP3, and consumes 500 mW. The transmitter chip includes a power amplifier, image-reject driver, IF-to-RF upmixer, IF amplifier strip, quadrature baseband-to-IF mixers, PLL, and frequency tripler. It achieves output P1dB of 10 to 12dBm, Psat of 15 to 17 dBm, and consumes 800 mW. The chips have been packaged with planar antennas, and a wireless data link at 630 Mb/s over 10 m has been demonstrated

Efficient yellow-light generation by frequency doubling a narrow-linewidth 1150 nm ytterbium fiber oscillator.

Abstract: A linearly polarized, narrow-linewidth, diode-pumped, Yb-doped silica-fiber oscillator operating at 1150 nm was frequency doubled to produce 40 mW of 575 nm radiation. The oscillator generated 89 mW of cw linearly polarized output power and was tunable over 0.80 nm. The laser output was coupled to a periodically poled LiNbO3 waveguide that converted 67% of the coupled power to the yellow. The system was fully integrated, with no free-space optics, and had an overall optical-to-optical efficiency of 7.0% with respect to the incident diode-laser pump power.

A 40-GHz Frequency Divider in 90-nm CMOS Technology

Abstract: This paper presents the design of a high-speed wide-band frequency divider. The divider core is formed with a low voltage swing current mode logic (CML) structure, which enables high frequency operation at very low power dissipation. The divider exhibits very wide locking range from 4GHz - 41GHz, and it has an input sensitivity of -31dBm at 30GHz. The divider core draws only 750?A from a 1.2V supply. Post layout simulation results in 90-nm CMOS technology are provided.

A 120-MHz–1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling

Abstract: A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-mum CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07 mm2 and has a peak-to-peak jitter of plusmn6.6 ps at 1.3 GHz

Single chip gsm/edge transceiver architecture with closed loop power control

Abstract: A single chip GSM/EDGE transceiver comprises a fully differential receive chain, a subharmonic mixer in the receive chain, the subharmonic mixer configured to receive a radio frequency (RF) input signal and a local oscillator (LO) signal that is phase-shifted by a nominal 45 degrees, and a synthesizer having a voltage controlled oscillator and having at least one frequency divider to generate desired transmit and receive LO signals. The transceiver also comprises a transmitter having a closed power control loop, and a harmonic rejection modulator, the use thereof made possible by a frequency plan designed to allow the synthesizer to develop the transmit and receive LO signals without a frequency multiplier.

A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction

Abstract: A low phase noise, delay-locked loop-based programmable frequency multiplier, with the multiplication ratio from 13 to 20 and output frequency range from 900 MHz to 2.9 GHz, is reported in this brief. A new switching control scheme is employed in the circuit to enable the capability of locking to frequencies either above or below the start-up frequency without initialization. To reduce the spurious output power level, a low-bandwidth auxiliary loop [period error compensation loop (PECL)] is employed to compensate for the output period error caused by the phase realignment errors. This frequency multiplier is implemented in TSMC 0.18-mum CMOS technology and measured with a synthesized frequency source. A significant reduction of the output spurs from -23 to -46.5 dB at 1.216 GHz is achieved by enabling the PECL. The measured cycle-to-cycle timing jitter at 2.16 GHz is 1.6 ps (rms) and 12.9 ps (pk-pk), and the phase noise is -110 dBc/Hz at 100-kHz offset with a power consumption of 19.8 mW at a 1.8-V power supply

The design and analysis of a DLL-based frequency synthesizer for UWB application

Abstract: A delay-locked loop (DLL)-based frequency synthesizer is designed for the ultrawideband (UWB) Mode-1 system. This frequency synthesizer with 528-MHz input reference frequency achieves less than 9.5-ns settling time by utilizing wide loop bandwidth and fast-settling architecture. Additionally, a discrete-time model of the DLL and an analytical model of phase noise of the delay line are proposed in this work. Experimental results show great consistency with predicted settling time and phase noise. The circuit has been fabricated in a 0.18-/spl mu/m CMOS technology and consumes only 54 mW from a 1.8-V supply. It exhibits a sideband magnitude of -35.4 dBc and -120-dBc/Hz phase noise at the frequency offset of 1 MHz.

Switching controller for resonant power converter

Abstract: An integrated control circuit for a resonant power converter includes a minimum-frequency programming circuit connected a first resistor to program a minimum switching frequency of the power converter A feedback circuit is coupled to a feedback terminal to receive a feedback signal for generating an adjustment signal A maximum-frequency programming circuit connects a second resistor to determine a maximum switching frequency in response to the adjustment signal An oscillator is coupled to the minimum-frequency programming circuit and the maximum-frequency programming circuit to generate an oscillation signal for determining the switching frequency of the power converter A feed-forward circuit is connected to a feed-forward terminal to receive a feed-forward signal represents the input voltage of the power converter The switching frequency is increased in response to decrease of the feedback signal, and the switching frequency is increased in response to the increase of the feed-forward signal

Method and apparatus to reduce audio frequencies in a switching power supply

Abstract: An example power supply regulator includes an energy transfer element, a switch, and a controller. The controller includes a switch signal generator, a modulation circuit, and a multi-cycle modulator circuit. The modulation circuit modulates the period of a modulation switching signal when an equivalent switching frequency is greater than a reference frequency and fixes the switching period when the equivalent switching frequency is less than the reference frequency. The multi-cycle modulator circuit enables the switch signal generator to provide a switch signal uninterrupted if the equivalent switching frequency is greater than the reference frequency and disables the switch signal generator for a first time period and then enables the switch signal generator for a second time period when the equivalent frequency is less than the reference frequency. The multi-cycle modulator circuit varies the first time period to regulate the output.

A 14-band Frequency Synthesizer for MB-OFDM UWB Application

Abstract: A 14-band frequency synthesizer for UWB application is realized in a 0.18 mum CMOS process. It uses two PLLs and three mixers. The unwanted spurs due to frequency mixing are at least 35dB lower than the output carriers by using a quadrature divide-by-3 circuit and a 2-stage single-sideband mixer. The core circuit area is 1.5 mm2 and the power consumption is 160mW

G-band metamorphic HEMT-based frequency multipliers

Abstract: Two monolithic G-band active frequency multipliers have been designed and fabricated using coplanar-waveguide technology. The monolithic microwave integrated circuits are a frequency tripler for an output frequency of 140 GHz and a 110-220-GHz frequency doubler. The tripler demonstrates a maximum conversion gain of -11 dB for an input power of 9 dBm, whereas the doubler achieves a conversion gain of -7 dB for a 2.5-dBm input signal. The circuits have been realized using two InAlAs/InGaAs-based metamorphic high electron-mobility transistor processes with different gate lengths of 100 and 50 nm, respectively.

A 5.25-GHz CMOS folded-cascode even-harmonic mixer for low-voltage applications

Abstract: This paper presents a 5.25-GHz folded-cascode even-harmonic mixer (FEHM) for low-voltage applications. This FEHM employs the folded technique to reduce the headroom voltage, a current reuse circuit in the RF stage to improve its linearity, and the frequency-doubling technique in the local oscillator (LO) stage to produce an LO double-frequency signal. In addition, the proposed technique exhibits the advantage of high conversion gain. In order to demonstrate the benefits and optimize the circuit design, the theoretical studies of conversion gain, linearity, and noise performance are described. For measurement, the proposed FEHM possesses conversion gain of 8.3 dB, third-order input intercept point (IIP/sub 3/) of 0.03 dBm, and second-order input intercept point (IIP/sub 2/) of 31.2 dBm under the supply voltage of 0.9 V and LO power of 5.5 dBm. The power consumption of the proposed mixer is about 4.95 mW at an IF frequency of 500 kHz.

Design and Testing of Frequency-Selective Surfaces on Silicon Substrates for Submillimeter-Wave Applications

Abstract: A new class of frequency-selective surfaces (FSSs), to be used as quasi-optical filters for harmonic suppression in submillimeter-wave frequency multipliers, is proposed and experimentally verified. The FSSs consist of two-dimensional aperture arrays and are made from microstructured aluminum on electrically thick, high-resistivity silicon substrates. This leads to a very good mechanical stability, reasonably low insertion loss, and permits manufacture of the structure by using standard processes available from the semiconductor industries. This paper presents the design, fabrication, and testing of two sets of prototypes, the former with a passband at 300 GHz and a stopband at 450 GHz and the latter with a passband at 600 GHz and a stopband at 750 GHz. For both frequency ranges, FSSs with rectangular slots and with dogbone-shaped holes have been designed by using the method of moments/boundary integral-resonant mode expansion method. The effect of ohmic and dielectric losses has been determined by using the commercial code HFSS. Several prototypes have been fabricated, and measured by terahertz time-domain spectroscopy and continuous wave measurements, showing high reproducibility of the machining process, insertion loss between 1.0 and 1.6 dB, and stopband attenuation larger than 30 dB. Finally, we demonstrate that the incidence angle can be used as a degree of freedom for fine tuning the stopband, without practically changing the frequency response in the passband

A fast-settling PLL frequency synthesizer with direct frequency presetting

Abstract: A PLL frequency synthesizer with frequency presetting is implemented in a 0.35mum CMOS process and occupies 0.4mm2. The output frequency is between 560 and 820MHz, the supply is 3.3V, the measured settling time is <10mus and the phase noise is -85dBe/Hz at 10kHz offset. The synthesizer can automatically compensate for frequency variation with temperature

Downconverter and upconverter

Abstract: A downconverter and upconverter are provided which can obtain a sufficient image rejection ratio in a low-Intermediate Frequency (IF) scheme while reducing power consumption and can suppress Error Vector Magnitude (EVM)-related degradation in a zero-IF scheme A complex-coefficient transversal filter rejects one side of a positive or negative frequency, and converts a Radio Frequency (RF) signal to a complex RF signal configured by real and imaginary parts A local oscillator outputs a real local signal with a set frequency A half-complex mixer, connected to the complex-coefficient transversal filter and the local oscillator, performs a frequency conversion process by multiplying the complex RF signal output from the complex-coefficient transversal filter and the real local signal output from the local oscillator, and outputs a complex signal of a frequency separated by the set frequency from a frequency of the RF signal

Method and system for filter calibration using fractional-N frequency synthesized signals

Abstract: A method and system for filter calibration using fractional-N frequency synthesized signals are presented. Aspects of the method may include generating an LO signal by a PLL circuit within a chip. A reference signal may be generated based on the generated LO signal and a synthesizer control signal. A frequency response for a filter circuit integrated within the chip may be calibrated by adjusting parameters associated with the filter circuit based on the generated LO signal. Aspects of the system may include a single-chip multi-band RF receiver that enables generation of a LO signal by a PLL circuit within the single-chip, and enables calibration of a frequency response for a filter circuit integrated within the chip. A reference signal may be generated based on the generated LO signal and a synthesizer control signal. The frequency response may be calibrated by adjusting the filter based on the generated reference signal.

120-GHz Tx/Rx Waveguide Modules for 10-Gbit/s Wireless Link System

Abstract: This paper describes the development of wavegude modules for 120-GHz wireless applications. The MMIC in the modules were fabricated using 0.1-mum-gate InP-HEMTs and coplanar waveguides. The transmitter (Tx) module contains a Tx MMIC and a multiplier MMIC for carrier generation. The Tx MMIC contains a frequency doubler, ASK modulator, and an amplifier. Output power of the Tx module is 0 dBm. The receiver (Rx) module contains a Rx MMIC with a low-noise amplifier and ASK demodulator. For high-power operation of transmitter, we developed a power amplifier (PA) waveguide module that attaches to the Tx module. This PA module contains one-chip PA MMIC, and has 13-dBm output power with associated gain of 10.5 dB at 125 GHz. A back-to-back test of the Tx/Rx modules with and without the PA module have shown it to be fully functional at 10-Gbit/s data rate with BER = 1e-10 at -34.5-dBm and -36.1-dBm input powers for the receiver, respectively

Radio frequency particulate sensing system

Abstract: A particulate sensing system for a particulate trap including a radio frequency transmit circuit and a radio frequency receive circuit is disclosed. The transmit circuit may include a wideband signal generator configured to produce a wideband radio frequency signal and a wideband radio frequency amplifier, coupled to the wideband signal generator. The transmit circuit may include a transmit antenna coupled to the wideband radio frequency amplifier and configured to propagate the wideband radio frequency signal through a filter medium. The receive circuit may include a receive antenna configured to receive the wideband radio frequency signal that has been propagated through the filter medium, and a bandpass filter coupled to the receive antenna and configured to limit a frequency range of the received wideband radio frequency signal. The receive circuit may include a radio frequency power sensing device coupled to the bandpass filter and configured to sense a power level of the received wideband radio frequency signal and configured to output a direct current voltage proportional to the total power received across an operating frequency range of the radio frequency power sensing device.

Simulation-assisted design and analysis of varactor-based frequency multipliers and dividers

Abstract: Varactor-based circuits, used for frequency conversion, have the advantages of a simple topology, high efficiency, reasonable bandwidth, and good isolation of the input signal. However, they often exhibit spurious oscillations, which complicate the design and limit their applicability. In the case of frequency dividers, the operation bands are bounded by bifurcation phenomena. In this paper, the behavior of these circuits is investigated with stability-analysis and bifurcation-detection capabilities through harmonic-balance techniques. The techniques are applied for the design of a frequency tripler, a frequency divider-by-3 and a fractional-order frequency divider-by-3/2. Good experimental behavior has been obtained in all cases. The discrepancies with the simulated results have been found to be due to the high tolerances of the lumped elements.

A 12-36GHz PHEMT MMIC balanced frequency tripler

Abstract: A novel configuration of balanced frequency InGaAs pseudomorphic high electron mobility transistor (PHEMT) monolithic microwave integrated circuit (MMIC) tripler is proposed. A resonant LC filter is used to eliminate the fundamental frequency and a phase delay line is employed to suppress the second harmonic. The separation of the independent phase shifters makes the tripler more compact and flexible. The conversion loss of the tripler operating from 12 to 36GHz is less than 9.4dB at 9-dBm input power. As compared to the third-harmonic frequency, the fundamental frequency is suppressed more than 21.4dB while for the second harmonic is more than 22.3dB at 36GHz

High frequency signal transmission device

Abstract: PROBLEM TO BE SOLVED: To provide a high frequency signal transmission device capable of efficiently transmitting a high frequency signal between circuits on different planes. SOLUTION: In a high frequency signal transmission device 1 being a device for transmitting a high frequency signal between circuits on different planes P-a and P-b, a resonator 2 having a structure having a part of a closed curve line opened or a spiral structure and an input/output line 3 which is connected to the resonator 2 and inputs/outputs the high frequency signal to/from the resonator 2 are formed on each plane, and the high frequency signal is transmitted by electromagnetic coupling between resonators 2 formed on both planes. COPYRIGHT: (C)2008,JPO&INPIT

A 40-GHz static frequency divider with quadrature outputs in 80-nm CMOS

Abstract: The implemented static frequency divider provides quadrature (Q) clock outputs and divides frequencies up to 44GHz. The core divider circuit consists of two current-mode logic (CML) latches and consumes 3.2mW from a 1.1-V supply. The divided outputs result in a peak-to-peak and rms jitter of 6.3 and 0.8ps, respectively, and the maximum phase mismatch between the in-phase (I) and Q-outputs amounts to 1ps at an input frequency of 40GHz. The high division frequency is achieved by employing resistive loads, inductive peaking, and optimizing the circuit layout for reduced parasitic capacitances in the latches. The core divider consumes a chip area of 30mumtimes40mum only

Effects of nonlinear feedback in the frequency domain

Abstract: A simple methodology to evaluate harmonic distortion in the frequency domain for circuits and systems made up of a nonlinear high-gain path with a nonlinear feedback network is presented. The approach provides compact closed-form expressions which constitute a direct extension of the classic ones valid at dc. The result improve our understanding of nonlinear frequency behavior in general feedback circuits and can even be used in manual design. The accuracy of the equations obtained was evaluated by comparison with computer simulations and measurements on an example circuit. Simulated and experimental data highly agree with the theoretical model.

A frequency-doubled laser system producing ns pulses for rubidium manipulation

Abstract: We have constructed a pulsed laser system for the manipulation of cold 87Rb atoms. The system combines optical telecommunications components and frequency doubling to generate light at 780 nm. Using a fast, fibre-coupled intensity modulator, we sliced output from a continuous laser diode into pulses with a length between 1.3 and 6.1 ns and a repetition frequency of 5 MHz. These pulses are amplified using an erbium-doped fibre amplifier, and frequency-doubled in a periodically poled lithium niobate crystal, yielding a peak power up to 12 W. Using the resulting light at 780 nm, we demonstrate Rabi oscillations on the F=2,mF=+2↔F′=3, m′F=+3-transition of a single 87Rb atom.

Doppler-free spectroscopy using a continuous-wave optical frequency synthesizer

Abstract: A continuous-wave (cw) optical frequency synthesizer is demonstrated by using a monolithic-type cw optical parametric oscillator (cw-OPO) and an optical frequency comb. The cw-OPO is phase locked to an optical frequency comb that is phase locked to an atomic clock. The output frequency of the cw-OPO is frequency shifted with an electro-optic modulator, which makes it possible to tune the frequency continuously over 10 GHz. Furthermore, Doppler-free spectroscopy is performed using the optical frequency synthesizer for a cesium D1 line at 895 nm. The observed linewidth of 5 MHz is the natural linewidth of cesium. The center frequency of the line is consistent with a previous report.

Feed forward amplifier for multiple frequency bands

Abstract: The present invention has for its object to provide, in an environment where plural radio systems coexist, a feed forward amplifier for multiple frequency bands, capable of adaptively selecting the frequency band which is used. The feed forward amplifier of the present invention comprises a distortion detection circuit and a distortion elimination circuit and has first and second variable frequency band extractors 25 a and 25 b provided in series with respective vector adjustment paths 21 a and 21 b. Also, the feed forward amplifier comprises a frequency band controller which varies the frequency band of variable frequency band extractors 25 a and 25 b and has been designed, by changing the frequency band of first and second variable frequency band extractors 25 a and 25 b in response to a frequency switching request from the outside, to be able to adaptively control the frequency band in which distortion is compensated.

A low-phase-noise voltage-controlled oscillator for 17-GHz applications

Abstract: A silicon bipolar voltage-controlled oscillator (VCO) for 17-GHz applications is presented. The VCO is composed of a core oscillating at 9GHz followed by a frequency doubler. It adopts a transformer-based topology to obtain both wide tuning range and low noise performance. The VCO exhibits a tuning range of 4.1GHz from 16.4 to 20.5GHz and a phase noise as low as -109dBc/Hz at a 1-MHz frequency offset from a carrier of 18.5GHz.

High frequency compression integration

Abstract: A speech enhancement system that improves the intelligibility and the perceived quality of processed speech includes a frequency transformer and a spectral compressor. The frequency transformer converts speech signals from the time domain to the frequency domain. The spectral compressor compresses a pre-selected portion of the high frequency band and maps the compressed high frequency band to a lower band limited frequency range. The speech enhancement system may be built into, may be a unitary part of, or may be configured to interface other systems that process audio or high frequency signals.

Coherent frequency modulated continuous wave radar

Abstract: A frequency modulated continuous wave (FMCW) radar is described. The radar includes a first discriminator for receiving a portion of the swept frequency signal generated by a frequency sweep generator and for producing a reference difference-frequency signal of frequency equal to the difference between the frequency of the swept frequency signal and the frequency of a time displaced swept frequency signal derived from the swept frequency signal. An analogue-to-digital converter is provided for sampling the target difference-frequency signal at a rate derived from the frequency of the reference difference-frequency signal. A processor ( 88 ) for determining frequency components of the digitized target difference-frequency signal is arranged to determine for at least one frequency component of the digitized target difference-frequency signal any phase difference between frequency sweeps of said swept frequency signal. The radar may be used for detecting foreign object debris (FOD) on runway surfaces and the like. A corresponding method of operating an FMCW radar is also described.

Configuration and controlling method of fractional-N PLL having fractional frequency divider

Abstract: The provided fractional frequency divider includes a divider controlling unit for generating a divider selection signal in response to a dual-edge triggering of an input signal and a frequency dividing unit coupled to the divider controlling unit for dividing the frequency of the input signal by one of an integer and a fractional dividers in response to the dual-edge triggering and the divider selection signal to generate the output signal of the fractional frequency divider. An operation of the frequency dividing unit is not suppressed when the integer divider is employed, the operation of the frequency dividing unit is not suppressed for a period of the input signal and is suppressed for half of that period, and this cycle is kept on recurring when the fractional divider is employed. The fractional-n PLL having the fractional frequency divider is also provided.