Showing papers on "Frequency multiplier published in 2018"

Fully Integrated Single-Chip 305–375-GHz Transceiver With On-Chip Antennas in SiGe BiCMOS

Abstract: A fully integrated single-chip transceiver (TRX) with on-chip antennas for transmitting and receiving signals within a continues frequency range from 305 to 375 GHz is presented. The radio-frequency (RF) and local oscillator signals are generated using a wideband push–push voltage-controlled oscillator, a three-stage power amplifier, and a frequency doubler. A heterodyne receiver using a fundamental mixer converts the received RF signal to an intermediate frequency (IF) signal, which drives an IF amplifier. Additionally, a divide-by-64 frequency divider is integrated to provide a low-frequency output for measurement purposes and to enable later the addition of a phase-locked loop for frequency stabilization and synthesis. A 130-nm silicon–germanium BiCMOS process with $f_t/f_{\max}$ = 250 GHz/370 GHz is used. The TRX chip is wire bonded to a printed circuit board and a TPX (Polymethylpentene) lens is placed on top of the chip for focusing the radiation. At a frequency of 343 GHz, the measurements show an effective isotropic radiated power of 18.4 dBm, a phase noise of $-$ 79 dBc/Hz@1 MHz, and an IF conversion gain of 28 dB. The obtained tuning bandwidth of 70 GHz is the highest reported so far for fully integrated TRXs.

A 219-to-231 GHz Frequency-Multiplier-Based VCO With ~3% Peak DC-to-RF Efficiency in 65-nm CMOS

Abstract: Signal sources at mm-wave and (sub-)terahertz frequencies in CMOS can be classified into two broad categories: harmonic oscillators and oscillators that are based on the frequency multiplication of fundamental sources. This paper shows that frequency-multiplier-based sources potentially have a higher dc-to-RF efficiency than do the popular harmonic oscillators in 65-nm CMOS. To improve the power efficiency of CMOS signal sources that operate near or above the cutoff frequency of the device, design factors including the harmonic current efficiency, the effective output conductance, and the passive losses should be carefully tailored. An architecture is proposed in which: 1) the core voltage-controlled oscillator is optimized to efficiently generate a strong fundamental harmonic; 2) separate class-C frequency doublers are utilized to decouple fundamental signal generation and harmonic extraction and to reduce conductance loss; and 3) doubler circuits are separately optimized to simplify the output matching and power combining network, and hence avoid long and lossy transmission lines. A circuit prototype shows a measured peak output power and dc-to-RF efficiency of 3 dBm and 2.95%, respectively.

A Low-Integrated-Phase-Noise 27–30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers

Abstract: An ultra-low-phase-noise injection-locked frequency multiplier (ILFM) for millimeter wave (mm-wave) fifth-generation transceivers is presented. Using an ultra-low-power frequency-tracking loop (FTL), the proposed ILFM is able to correct the frequency drifts of the quadrature voltage-controlled oscillator of the ILFM in a real-time fashion. Since the FTL is monitoring the averages of phase deviations rather than detecting or sampling the instantaneous values, it requires only 600 $\mu \text{W}$ to continue to calibrate the ILFM that generates an mm-wave signal with an output frequency from 27 to 30 GHz. The proposed ILFM was fabricated in a 65-nm CMOS process. The 10-MHz phase noise of the 29.25-GHz output signal was −129.7 dBc/Hz, and its variations across temperatures and supply voltages were less than 2 dB. The integrated phase noise from 1 kHz to 100 MHz and the rms jitter were −39.1 dBc and 86 fs, respectively.

D-Band Frequency Quadruplers in BiCMOS Technology

Abstract: This paper presents two D-band frequency quadruplers (FQs) employing different circuit techniques. First FQ is a 129–171-GHz stacked Gilbert-cell multiplier using a bootstrapping technique, which improves the bandwidth and the conversion gain with respect to the conventional topology. Stacked architecture enables current reuse for the second frequency doubler resulting in a compact and energy-efficient design. The circuit reaches 3-dB bandwidth of 42 GHz, which is the highest among similar reported quadruplers. It achieves 2.2-dBm saturated output power, 5-dB peak conversion gain, and 1.7% peak DC-to-RF efficiency. The stacked FQ occupies 0.08 mm2 and consumes 22.7 mA from 4.4-V supply. Second presented circuit is a transformer-based injection-locked FQ (T-ILFQ) employing an E-band push–push voltage-controlled oscillator (PP-VCO). The VCO is a self-buffered common-collector Colpitts oscillator with a transformer formed on emitter inductors. Proposed configuration does not reduce the tuning range of the VCO, thus providing wide locking range and high sensitivity with respect to the injected signal. The T-ILFQ achieves 21.1% locking range, which is the highest among other reported injection-locked frequency multipliers. The peak output power is −4 dBm and the input sensitivity reaches −22 dBm. The circuit occupies 0.09 mm2 and consumes 14.8 mA from 3.3-V supply.

A Wideband SiGe BiCMOS Frequency Doubler With 6.5-dBm Peak Output Power for Millimeter-Wave Signal Sources

Abstract: This paper presents a balanced frequency doubler with 6.5-dBm peak output power at 204 GHz in 130-nm SiGe BiCMOS technology ( $f_{T}/f_{\max }=210$ /250 GHz). To convert the single-ended input signal to a differential signal for balanced operation, an on-chip transformer-based balun is employed. Detailed design procedure and compensation techniques to lower the imbalance at the output ports, based on mixed mode S parameters are proposed and verified analytically and through electromagnetic simulations. The use of optimized harmonic reflectors at the input port results in a 2-dBm increase in output power without sacrificing the bandwidth of interest. The measured conversion loss of the frequency doubler is 9 dB with 6-dBm input power at 204-GHz output. The measured peak output power is 6.5 dBm with an on-chip power amplifier stage. The 3-dB output power bandwidth is measured to be wider than 50 GHz (170–220 GHz). The total chip area of the doubler is 0.09 mm2 and the dc power consumption is 90 mW from a 1.8-V supply, which corresponds to a 5% collector efficiency.

Beat Frequency Oscillation Analysis for Power Electronic Converters in DC Nanogrid Based on Crossed Frequency Output Impedance Matrix Model

Abstract: The interaction of power electronic converters in a microgrid can introduce system instability and power quality issues Existing investigations focus on interactions either in low-frequency regions, such as the constant power load, or in very high-frequency regions like electromagnetic interference However, interactions of power converters around their switching frequency range are not included In fact, the interaction of dc–dc converters with different switching frequencies can introduce beat frequency oscillation in certain cases Since additional frequency component (beat frequency) is generated, traditional impedance concept is no longer the tool for beat frequency oscillation analysis and new models need to be developed In this paper, a crossed frequency output impedance matrix model is proposed to describe the terminal characteristics of a dc–dc converter around its switching frequency range A high-frequency equivalent circuit model for the converter is then developed to predict the beat frequency oscillation in parallel and cascaded systems, which results from the interaction of power converters with different switching frequencies Finally, design guidelines are proposed to avoid potential beat frequency oscillation in a dc nanogrid Experimental results for both parallel and cascaded systems validate the accuracy and effectiveness of the proposed prediction method and design guidelines

A −31dBc integrated-phase-noise 29GHz fractional-N frequency synthesizer supporting multiple frequency bands for backward-compatible 5G using a frequency doubler and injection-locked frequency multipliers

Abstract: To address the increasing demand for high-bandwidth mobile communications, 5G technology is targeted to support data-rates up to 10Gb/s. To reach this goal, one of challenging tasks for wireless transceivers is to generate millimeter-wave (mmW) band Lo signals that have an ultra-low integrated phase noise (IPN). The IPN of an LO signal should be reduced to less than −30dBc to satisfy the EVM requirements of high-order modulations, such as 64-QAM. Figure 23.1.1 shows the frequency spectrum for cellular systems, including existing bands below 6GHz and new mmW bands for 5G. A key goal of the evolution of mobile communications is to ensure interoperability with past-generation standards, and this is expected to continue for 5G. Thus, LO generators eventually will be designed to cover existing bands as well as mmW bands. There are many PLLs that can generate mmW signals directly [1,2], but their ability to achieve low IPN is limited. This is because they are susceptible to increases in in-band phase noise due to their large division numbers and out-of-band phase noise due to the low Q-factors of mmW VCOs. They also require a significant amount of power to operate high-frequency circuits, such as frequency dividers. In addition, they must divide frequencies again to support bands below 6GHz, resulting in the consumption of additional power.

300-GHz CMOS QPSK transmitter for 30-Gbps dielectric waveguide communication

Abstract: A 300-GHz 30-Gbps QPSK transmitter is demonstrated in 65-nm CMOS. The transmitter consists of an on-chip multi-mode modulator, an injection locked quadrature oscillator, a 40-GHz bandwidth power amplifier with constant gain and group delay, a 4X frequency multiplier chain to generate a 165-GHz LO signal for a double balanced up-conversion mixer that generates the output at 300 GHz. The transmitter without equalization consumes 180mW with an energy efficiency of 6 pJ/bit.

Passive Harmonic RFID System for Buried Assets Localization.

Abstract: A passive harmonic tag for buried assets localization is presented for utility localization. The tag design is based on a dual-polarized patch antenna at Ultra High Frequency (UHF) band. One of its feeders is connected to a frequency doubler based on a Schottky diode that generates the second harmonic, which is transmitted using a linear-polarized patch tuned at this frequency. The power received at the other feeder of the dual-polarized antenna is harvested by an RF to DC converter based on a five-stage voltage multiplier whose energy is used to bias a low-power quartz oscillator that modulates the output of the doubler. The different parts of the system are presented, and the theoretical read range is estimated as a function of the soil composition and the water content. A low-cost reader based on a software defined radio is also presented. Finally, experiments with a prototype of the tag are performed for different soil conditions.

A Wide-Input-Range High-Efficiency Step-Down Power Factor Correction Converter Using a Variable Frequency Multiplier Technique

Abstract: This paper demonstrates a two-stage implementation of a step-down power factor preregulator design that achieves a high efficiency across the entire universal input voltage range ( $\text{85}\text{--}\text{265}\,\textrm {V}_{\textrm {rms}}$ ) for an offline power supply application. In this implementation, a resonant LLC converter supplies power to a boost converter operating in a continuous conduction mode. A variable frequency multiplier technique is used in a resonant LLC converter stage to provide different dc gains and compress the effective input voltage range. The efficiency performance achieved is flatter and higher than other conventional offline power converter design consisting of a boost power factor correction circuit followed by a resonant LLC converter, whose efficiency tends to drop significantly at low-line input voltages. The proposed circuit allows MOSFETs with lower voltage ratings and better conduction/switching characteristics to be used in both converter stages. Both of the LLC stage and boost circuit can be better optimized due to the compressed operation range and better semiconductor switches. A scaling law of power losses versus breakdown voltage requirement for boost circuit under the condition of the same output power is presented. Experimental results demonstrated a flatter high efficiency performance across a wide input range.

Integrated 240-GHz Dielectric Sensor With dc Readout Circuit in a 130-nm SiGe BiCMOS Technology

Abstract: This paper presents a high-integration miniaturized dielectric spectroscopy system for sensing the change of permittivity at 240 GHz in the SiGe BiCMOS technology. The sensor features a transducer with a resonator to perform bandpass frequency response, whose complex value of $S_{21}$ is varied with the permittivity of the sample under test. This variation can be detected and recorded as the change of amplitude and phase of the 240-GHz in-phase and quadrature direct conversion mixer. An external 30-GHz source is employed with cascade frequency multiplier chain to deliver a signal through the system with a wide tuning range of 215–245 GHz. An additional probe is employed to carry the sample and implement chip measurements on the probe station. The sensing function of this system is performed with the leaded wire as a metallic sample to be placed on the top of the transducer. Based on the measured dc output voltage changes, the calculated magnitude and phase of IQ signal in the 215–245-GHz range are used to estimate the complex permittivity change of MUTs. This dielectric spectroscopy system is also suitable for sensing the complexy permittivity change at higher frequencies in the future terahertz Lab-on-Chip measurements.

Amplitude and Frequency Estimation of Exponentially Decaying Sinusoids

Abstract: An online method for amplitude and frequency estimation of exponentially decaying sinusoids is proposed with a moving-window discrete Fourier transform (MWDFT) filter and frequency-locked loop. The tuned filter characteristics of MWDFT is modified into more flat characteristic around the center frequency with negative feedback, which increases the bandwidth of the filter. An adaptive sampling pulse adjustment mechanism is incorporated in the proposed structure for online estimation of frequency. Hence, the frequency error was exploited to achieve synchronization between in-phase component of MWDFT and input signal of estimation. The amplitude is estimated in online from the in-phase and quadrature-phase components of MWDFT. The performance of the proposed method is compared with the existing techniques and experimentally validated on single-link flexible manipulator system for the online estimation of frequency and amplitude of tip deflection signal. The experimental investigation prove that the proposed online technique performs well over the existing techniques.

A 180-GHz Schottky Diode Frequency Doubler With Counter-Rotated $E$ -Fields to Provide In-Phase Power-Combining

Abstract: This letter reports on the first demonstration of a power-combined Schottky diode frequency doubler that uses counter-rotated $E$ -fields at the output of two frequency doublers to enable in-phase $H$ -plane power-combining. The single chip integrated circuit comprises of a four-anode structure on a 20- $\mu \text{m}$ -thick GaAs substrate that when used individually demonstrates a peak efficiency of 34% and the maximum output power of 109 mW at 180 GHz. In a power-combined configuration, the frequency doubler with counter-rotated $E$ -fields exhibits a 3-dB bandwidth of 10% and a peak conversion efficiency of 37% for input powers between 150 and 200 mW. This doubler delivers 130-mW output power and 26% conversion efficiency for 500-mW input. The novel $H$ -plane power-combined frequency doubler is compared with the single-chip doubler to show the combining efficiency and the chip-to-chip variation for multiple circuit builds.

Truly Balanced K-Band Push-Push Frequency Doubler

Abstract: This paper presents a truly balanced push-push frequency doubler. The novel concept is based on two lumped quadrature couplers that provide a truly balanced signaling for two doubler cells. As a consequence, the output signal is inherently balanced and a lossy output transformer can be avoided. Hence, higher output power and efficiency can be achieved. As a proof of concept, a K-band doubler is implemented in a 65 nm CMOS technology. At 0 dBm input power, the circuit delivers 5 dBm output power with more than 6 % PAE. The chip draws 26 mA from a 1.2 V supply and the total chip area is 0.85×0.55 mnr2. The fundamental suppression is around 44 dBc. To the best of the authors knowledge, this is the first fully balanced push-push doubler and the achieved results exceed state-of-the-art performance. The concept is applicable to other technologies and frequencies as well.

Multi-format signal generation using a frequency-tunable optoelectronic oscillator

Abstract: A novel photonic approach for multi-format signal generation based on a frequency-tunable optoelectronic oscillator (OEO) is proposed using a dual-polarization quadrature phase shift-keying (DP-QPSK) modulator. The upper dual-parallel Mach-Zehnder modulator (DP-MZM) integrated in the DP-QPSK modulator is properly biased to serve as an equivalent phase modulator, which functions in conjunction with a phase-shifted fiber Bragg grating (PS-FBG) in the OEO loop as a high-Q microwave photonic band-pass filter. The lower DP-MZM in the DP-QPSK modulator injected by the oscillation signal functions as a frequency multiplier, a phase-coded microwave signal generator or an optical frequency comb generator, respectively, with different signal injection methods. An experiment is performed. When the lower DP-MZM serves as a frequency multiplier, tunable frequency-doubled and quadrupled microwave signals up to 40 GHz are generated without using an optical notch filter; and if it functions as a phase-coded microwave signal generator, fundamental and frequency-doubled binary phase-coded microwave signals are generated with a tunable frequency. Furthermore, tunable five-line optical frequency combs are also generated using the compact system without an external RF source. The performance of the generated signals is also investigated.

Analog Circuit Applications Based on Ambipolar Graphene/MoTe2 Vertical Transistors

Abstract: The current integrated circuit (IC) technology based on conventional MOS-FET (metal-oxide-semiconductor field-effect transistor) is approaching the limit of miniaturization with increasing demand on energy. Several analog circuit applications based on graphene FETs have been demonstrated with less components comparing to the conventional technology. However, low on/off current ratio caused by the semimetal nature of graphene has severely hindered its practical applications. Here we report a graphene/MoTe2 van der Waals (vdW) vertical transistor with V-shaped ambipolar field effect transfer characteristics to overcome this challenge. Investigations on temperature dependence of transport properties reveal that gate tunable asymmetric barriers of the devices are account for the ambipolar behaviors. Furthermore, to demonstrate the analog circuit applications of such vdW vertical transistors, we successfully realized output polarity controllable (OPC) amplifier and frequency doubler. These results enable vdW heterojunction based electronic devices to open up new possibilities for wide perspective in telecommunication field.

A Compact Highly Efficient High-Power Ka-band SiGe HBT Cascode Frequency Doubler With Four-Way Input Transformer Balun

Abstract: A compact highly efficient high-power SiGe Ka-band balanced frequency doubler is presented. Using a compact single-footprint four-way transformer input balun, wideband matching, and high fundamental rejection were achieved simultaneously. A cascode topology with very low base impedance termination was utilized for stable operation and high-voltage swing at the output. Two cascode differential pairs form a common-centroid configuration, resulting strong enhancement in output power, power-added efficiency (PAE), fundamental rejection, and robustness to process and supply variation. The proposed Ka-band cascode balanced frequency doubler was implemented in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology. Measured results show 13-dBm output power with 22% peak PAE at 34 GHz for a −1-dBm input power. The 3-dB conversion gain bandwidth is from 25 to 40 GHz, fully covering Ka-band. Peak fundamental suppression is 74.5 dB at 33 GHz, and it is higher than 35 dB over Ka-band. No performance degradation is observed after 24-h RF stress test. To the author’s best knowledge, this paper has the highest efficiency, the highest output power/power density, the highest conversion gain without output buffers, and the higher or comparable fundamental rejection among any Si-based frequency doublers. Therefore, this doubler will be a promising solution for efficient and high-power local oscillator generation in 5G wireless phased-array communication system.

Design and Analysis of W-Band Injection-Locked Frequency Divider Using Split Transformer-Coupled Oscillator Technique

Abstract: A W-band injection-locked frequency divider (ILFD) with low-power and wide locking range is presented in this paper. The operation frequency and locking range are enhanced by using split transformer-coupled oscillator. The optimum bias and the size of the injection transistor are chosen to achieve wider locking range without increasing chip area and dc power consumption. The proposed ILFD is implemented in 90-nm CMOS and exhibits 25.4% locking range from 75.1 to 99 GHz at an input power of 0 dBm without any tuning mechanism. The core dc power consumption is 2.45 mW with a supply voltage of 0.7 V and the core chip size is $0.13 \times 0.2$ mm2.

A ZERO-Power Sensor Using Multi-Port Direct-Conversion Sensing

Abstract: This paper presents a class of zero-power microwave sensor architecture based on the direct-conversion principle to eliminate data processing at the Internet of Things sensors and provide unpowered nodes. A base station (BS) transmits a single tone signal at the frequency of $f_{0}$ /2 toward the sensing node using an antenna. At the node, an antenna receives the signal, and a passive frequency doubler makes the frequency twice. Then, a multi-port structure directly modulates the sensing data at the frequency of $f_{0}$ and sent back to the BS by an antenna. The multi-port circuit has one input, one output, and some loading ports. In this paper, a six-port modulator and four similar sensitive capacitive resonators are used. A pair of resonators senses the variation of a sample under test (SUT) while the other pair is covered by a reference or known material. At the BS, any quadrature receiver can be used to demodulate sensing data. Here, a similar six-port structure is used to extract data and find the SUT variations. An example one-node system is implemented at $f_{0} = 2.45$ GHz and evaluated by some standard SUTs. To support multiple nodes, a smart directional antenna is necessary at the BS, which also improves the overall efficiency of the system.

A 110-to-147 GHz Frequency Sixtupler in a 130 nm Sige Bicmos Technology

Abstract: The presented D-band sixtupler consists of a frequency tripler, a frequency doubler, as well as amplifiers. The optimum arrangement for those blocks is investigated. The analysis shows that the tripler should precede the doubler. Furthermore, to extend the bandwidth, an amplifier with an increasing gain versus frequency is applied, to compensate the gain decrease of the tripler. This wideband frequency sixtupler is designed and characterized in a 130 nm SiGe BiCMOS technology. This sixtupler has a bandwidth of 37 GHz (from 110 to 147 GHz), the maximum output power is 4.5 dBm, with a DC power consumption of 310 mW. The maximum power efficiency is 0.9%.

Design and Realization of Microwave Frequency Multiplier Based on Field Emission From Carbon Nanotubes Cold-Cathode

Abstract: This paper reports for the first time the theoretical analysis, design, and realization of a microwave (MW) frequency multiplier based on a field emission from carbon nanotube (CNT) cold-cathode. The nonlinear characteristic of field emission from CNT cold-cathode is utilized for generating field emission current with the harmonics of input signal and achieving frequency multiplication. We demonstrated both theoretically and experimentally that an MW electric field is capable of inducting current with harmonics from CNT cold-cathode and that a direct-current (dc) electric field can effectively increase the amplitudes of the harmonics. A reentrant resonant cavity structure was designed and fabricated to deliver the desired combined MW and dc electric fields onto CNT cold-cathode and realize the MW frequency multiplier. The device has the target second harmonic at a frequency of 1.868 GHz and a third harmonic at 2.802 GHz with a driving signal at frequency of 0.934 GHz. By simply increasing dc bias, a 12.43-dB increase of the amplitude of target second harmonic is successfully obtained. With such a device, directly modulated electron beam with MW frequency harmonics is obtained. Both the principle and the design can find applications in frequency tunable vacuum electron devices.

A 216–256 GHz fully differential frequency multiplier-by-8 chain with 0 dBm output power

Abstract: This work presents a fully differential wideband and low power 240 GHz multiplier-by-8 chain, manufactured in IHP's 130 nm SiGe:C BiCMOS technology with fT/fmax = 300/500 GHz. A single ended 30 GHz input signal is multiplied by 8 using Gilbert cell-based quadrupler and doubler, and then amplified with a wideband differential 3-stage cascode amplifier. To achieve wide bandwidth and optimize for power consumption, the power budget has been designed in order to operate the frequency multipliers and the output amplifier in saturation. With this architecture the presented circuit achieves a 3 dB bandwidth of 40 GHz, meaning a relative 3 dB bandwidth of 17%, and a peak saturated output power of 0 dBm. Harmonic rejections better than 25 dB were measured for the 5th, 6th, and 7th harmonics. It dissipates 255 mW from 3 V supply which results in drain efficiency of 0.4%, while occupying 1.2 mm2. With these characteristics the presented circuit suits very well as a frequency multiplier chain for driving balanced mixers in 240 GHz transceivers for radar, communication, and sensing applications.

Planar Multifrequency Wideband Bandpass Filters With Constant and Frequency Mappings

Abstract: A new planar filter design technique with constant and frequency mappings has been proposed for multifrequency wideband bandpass filters (BPFs). The constant mapping treats components in the $LC$ circuit (e.g., frequency invariant admittances, capacitors, and ideal inverters) as frequency dependent. It is consistent with practical planar circuits and caters to a wide frequency range. Following the classic single-to-multiband transformation, a new frequency mapping function is proposed by incorporating this constant mapping idea. With these two mapping functions, a direct relation between the $LC$ circuit and its microstrip counterpart is established. Therefore, the multifrequency wideband BPF is readily designed from a lowpassing $LC$ circuit to the transmission line circuit. A ladder-type Chebyshev filter and a trisection filter with the general Chebyshev response have been designed as examples. The first one is a dual-band case exhibiting a wide bandwidth for each passband. The second filter is a triple-band one showing a large frequency ratio between the first and third passband. Both examples experimentally validate the proposed constant and frequency mapping technique.

A 160 GHz Frequency Quadrupler based on Heterogeneous Integration of GaAs Schottky Diodes onto Silicon using SU-8 for Epitaxy Transfer

Abstract: An integrated frequency quadrupler operating at 160 GHz, producing 100 mW of output power, and achieving peak efficiency of 25.5% is described. The quadrupler design is based on prior art and consists of GaAs Schottky diodes with epitaxy transferred to a micromachined silicon carrier forming a heterogene-ously-integrated chip. A newly-developed fabrication process that eliminates high temperature annealing and utilizes SU-8 for adhesive bonding was employed to realize the circuit. The new process improves device yield and reliability compared to previous implementations.

A Balunless Frequency Multiplier With Differential Output by Current Flow Manipulation

Abstract: A balunless frequency doubler (FD) architecture which can provide differential output without any additional balun required is proposed in this paper. The architecture manipulates the desired second-harmonic currents around the doubler core by a multifunction network to avoid any leakage current path from the output current loop. Therefore, the output currents extracted from the same current loop can have the same amplitude and phase. As the output currents flow into and out of the same loads, respectively, the induced output voltages can be perfectly differential without needing to add a balun. A 60-GHz FD realized in a 90-nm CMOS technology is designed to verify the proposed FD architecture. The measured amplitude and phase imbalances of the differential output are only 0.2 dB and 0.5°, respectively, while providing −5.5-dB conversion gain at an output frequency of 60 GHz. The proposed FD only consumes 15.9 mW from a 1-V supply. The proposed doubler architecture can be theoretically extended to realize a frequency multiplier with a multiplication factor larger than 2.

A Bandwidth-Enhanced Differential LC-Voltage Controlled Oscillator (LC-VCO) and Superharmonic Coupled Quadrature VCO for K-Band Applications

Abstract: A novel varactor circuit exhibiting a wider tuning range and a new technique for quadrature coupling of LC-Voltage Controlled Oscillator (LC-VCO) is presented and validated on a 25 GHz oscillator. The proposed varactor circuit employs distribute-biased parallel varactors with a series inductor connected at both ends of the varactor bank to extend the tuning range of the oscillator. Similarly, the quadrature coupling is accomplished by employing the 2nd harmonic, explicitly generated in the stand-alone free-running differential oscillator using frequency doubler. As an example, the Differential VCO (DVCO) is tunable between 20 GHz and 31 GHz and exhibits the best Phase Noise (PN) of −100 dBc/Hz at 1 MHz offset frequency. Similarly, the Quadrature VCO (QVCO) covers 42% tuning bandwidth around 25 GHz oscillation frequency, which is significantly wider than other state-of-the-art VCOs at comparable frequencies. In addition, all the oscillators are designed in class-C to further improve their performances both in term of low power and low phase noise. The presented oscillators are designed using high-performance SiGe HBTs of the GlobalFoundries (GFs) 130 nm SiGe BiCMOS 8HP process. The presented DVCO and QVCO draw currents of approximately 10 mA and 21 mA, respectively from a 1.2 V supply.

8-PSK Upconverting Transmitter Using $E$ -Band Frequency Sextupler

Abstract: Operation of a frequency sextupler (X6) as a radio frequency (RF) $E$ -band upconverting transmitter is experimentally demonstrated An 8-phase-shift keying signal is digitally upconverted to 131-GHz intermediate frequency (IF) The resulting signal then goes through the X6 resulting in IF-to-RF upconversion to 786 GHz without the need for high-frequency oscillator, mixer, or modulator A simple one-sixth phase retardation of the baseband signal is used as digital predistortion A full signal processing chain is implemented at the digital receiver Techniques to mitigate remaining nonlinearity and worsened phase noise are considered

300-GHz Balanced Varactor Doubler in Silicon CMOS for Ultrahigh-Speed Wireless Communications

Abstract: This letter presents a 300-GHz varactor doubler suitable for ultrahigh-speed wireless communications. The doubler employs balance configuration to enhance the second harmonic efficiently. The proposed varactor doubler realized in TSMC 40-nm CMOS can be integrated with other CMOS components to generate millimeter-wave signals at 300-GHz frequency band. At the pumping frequency of 150 GHz and input power of 10 dBm, the doubler results in an output power of −4.6 dBm at 300 GHz. The doubler consumes no dc power while it occupies a chip area of $0.53~\text {mm}^{2}$ including probe pads.

A 5GHz 370fs rms 6.5mW clock multiplier using a crystal-oscillator frequency quadrupler in 65nm CMOS

Abstract: Phase noise performance of ring-oscillator-based (RO-based) clock multipliers is typically limited by oscillator noise. The most power-efficient method for improving the phase noise of such clock multipliers is by increasing the oscillator noise suppression bandwidth (F BW ). While F BW depends on the type of clock multiplier, the maximum achievable F BW is limited by the reference frequency (F ref ). For instance, in phase-locked loops (PLLs) F BW = F ref /10, while multiplying delay-locked loops (MDLLs) [1] and injection-locked clock multipliers (ILCMs) [2] can achieve F BW of F ref /4 and F ref /6, respectively. Exploiting this behavior, the MDLL in [1] and the ILCM in [2] achieved excellent performance at the expense of using a high-frequency low-noise reference (REF) clock and a small multiplication factor (N ref in MDLLs/ILCMs involves increasing the injection rate by using both the positive and negative edges of the REF clock [3, 4] but at the cost of making jitter/spurious performance susceptible to duty cycle errors in the REF clock. While [3] demonstrated an effective means to correct such errors, it still needed a relatively high F ref of 125MHz. In view of this, we present a method to quadruple the frequency of a conventional 54MHz Pierce XO and demonstrate its application using an RO-based ILCM achieving less than 370fs rms integrated jitter at a 5GHz output. The proposed quadrupler acts as a low noise XO frequency multiplier and can be used to increase the bandwidth of MDLLs and ring/LC-based integer-or fractional-N PLLs also.

A $Ka$ -Band SiGe Bootstrapped Gilbert Frequency Doubler With 26.2% PAE

Abstract: This letter presents a $Ka$ -band Gilbert frequency doubler (FD), in which the phase of the injected signal to switching transistors is adjusted to maximize the core conversion gain (CG) and power-added efficiency (PAE). It achieves a peak PAE of 26.2% and a peak CG of 21 dB at 28 GHz, without any output buffer. The FD provides a saturated output power of 11.9 dBm, a 3-dB bandwidth of 22–36 GHz, and a fundamental harmonic rejection of 32 dB. To the best of our knowledge, this FD achieves the highest CG and PAE among all reported Si-based FDs without output buffers.