Showing papers on "Mixed-signal integrated circuit published in 2009"

A Mixed-Signal Multichip Neural Recording Interface With Bandwidth Reduction

Abstract: We present a multichip structure assembled with a medical-grade stainless-steel microelectrode array intended for neural recordings from multiple channels. The design features a mixed-signal integrated circuit (IC) that handles conditioning, digitization, and time-division multiplexing of neural signals, and a digital IC that provides control, bandwidth reduction, and data communications for telemetry toward a remote host. Bandwidth reduction is achieved through action potential detection and complete capture of waveforms by means of onchip data buffering. The adopted architecture uses high parallelism and low-power building blocks for safety and long-term implantability. Both ICs are fabricated in a CMOS 0.18-mum process and are subsequently mounted on the base of the microelectrode array. The chips are stacked according to a vertical integration approach for better compactness. The presented device integrates 16 channels, and is scalable to hundreds of recording channels. Its performance was validated on a testbench with synthetic neural signals. The proposed interface presents a power consumption of 138 muW per channel, a size of 2.30 mm2, and achieves a bandwidth reduction factor of up to 48 with typical recordings.

A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction

Abstract: This paper presents a pipelined ADC with two fully integrated digital background calibration techniques: harmonic distortion correction (HDC) to compensate for residue amplifier gain error and nonlinearity and DAC noise cancellation (DNC) to compensate for DAC capacitor mismatches. It is the first IC implementation of HDC, and the results demonstrate that HDC and DNC together facilitate low-voltage operation and enable reductions in power dissipation relative to comparable conventional state-of-the-art pipelined ADCs. The pipelined ADC achieves a peak SNR of 70 dB and a -1 dBFS SFDR of 85 dB at a sample-rate of 100 MHz. It is implemented in a 90 nm CMOS process and consumes 130 mW from 1.2 V and 1.0 V analog and digital power supplies, respectively.

High performance sub-system design and assembly

Abstract: A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits, connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry.

Methods and systems for computer aided design of 3D integrated circuits

Abstract: Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

Integrated Power Electronic Converters and Digital Control

Abstract: Because of the demand for higher efficiencies, smaller output ripple, and smaller converter size for modern power electronic systems, integrated power electronic converters could soon replace conventional switched-mode power supplies. Synthesized integrated converters and related digital control techniques address problems related to cost, space, flexibility, energy efficiency, and voltage regulationthe key factors in digital power management and implementation. Meeting the needs of professionals working in power electronics, as well as advanced engineering students, Integrated Power Electronic Converters and Digital Control explores the many benefits associated with integrated converters. This informative text details boost type, buck type, and buck-boost type integrated topologies, as well as other integrated structures. It discusses concepts behind their operation as well specific applications. Topics discussed include:Isolated DC-DC converters such as flyback, forward, push-pull, full-bridge, and half-bridgePower factor correction and its applicationDefinition of the integrated switched-mode power suppliesSteady-state analysis of the boost integrated flyback rectifier energy storage converterDynamic analysis of the buck integrated forward converterDigital control based on the use of digital signal processors (DSPs)With innovations in digital control becoming ever more pervasive, system designers continue to introduce products that integrate digital power management and control integrated circuit solutions, both hybrid and pure digital. This detailed assessment of the latest advances in the field will help anyone working in power electronics and related industries stay ahead of the curve.

Adaptive circuits for the 0.5-V nanoscale CMOS era

Abstract: The V mins of logic, SRAM, and DRAM blocks were compared with a newly proposed methodology for evaluating V min based on speed variations, taking repair techniques into account. State-of-the-art 6T SRAM cells were then discussed in terms of V min and cell size. After that, many adaptive circuits and relevant technologies needed to break the 1V wall were proposed and evaluated, while taking the interconnect problem into account. Finally, 0.5V nanoscale LSIs including mixed signal LSIs were predicted to be feasible, if relevant devices and fabrication processes are developed.

Self checking and fault tolerant digital design

Abstract: During the process of development of any system, system reliability is of utmost importance. Specially when designing a processor, it is desired that a processor function correctly even in the presence of faults. This concept is commonly referred to as fault tolerance. The fault tolerant microprocessor systems used in safety critical applications need to be thoroughly validated during the design stages. As feature size reduces in future, there is an increased probability of transient and inter mittent faults. Now these systems on chip integrated circuits contain both digital and analog cores. Test cost for such mixed signal SOC is much higher than the digital SOC that allows the analog and digital cores to be tested. The analog cores are wrapped such that the test can performed using a digital test access mechanism. In our method, an analog test infrastructure is used which consists of test wrapper s and test access mechanism. Test wrappers isolate var ious modules from their surrounding circuitry during test. So the focus is on optimisation of a unified test access architecture that is used for digital and analo gue cores. We wrap each analog core by a pair of digital to analog converter and analog to digital converter. They convert analog core to virtual digital core which allow the use of digital testers to test the analog cores. This reduces the need for expensi ve mixed signal tester so that there is a reduction in the overall cost.

A 1 Gb/s Mixed-Signal Baseband Analog Front-End for a 60 GHz Wireless Receiver

Abstract: A low-power mixed-signal baseband analog front-end for 60 GHz, 1 Gb/s wireless communications has been implemented in a standard 90 nm CMOS process. The receiver is capable of operating under indoor multipath scenarios, resolving channels with up to 32 ns multipath delay spread. It uses mixed-signal equalization and carrier recovery in order to minimize the dynamic range requirements of the analog-to-digital converter circuitry. A new mixed-signal carrier phase recovery architecture, utilizing a replica tuning scheme employing Gilbert quad variable-gain amplifiers is introduced. The analog-to-digital converters use an active averaging technique that decouples the preamplifier gain from the averager input range, enabling enhanced suppression of mismatch-induced nonlinearities. These techniques enable a front-end with 6-bit linearity and dynamic range, while dissipating a low power consumption of 55 mW.

Planar Double-Gate Transistor

Abstract: Technological advances are mostly guided by performance constraints on digital and radio-frequency circuits. However, an integrated system on chip often involves analog parts. This chapter presents advantages and drawbacks of double gate CMOS technologies in analog design.

A 300Hz 19b DR capacitive accelerometer based on a versatile front end in a 5 th -order ΔΣ loop

Abstract: This paper presents a 5th-order ΔΣ capacitive accelerometer. The ΔΣ loop is implemented in mixed signal, the global 5th-order filter having a 2nd-order analog and a 3rd-order digital part. The system can be used with a wide range of sensors, because the mixed-signal front end is programmable. The ASIC developed comprises a voltage-mode preamplifier, two parallel demodulators implementing CDS, and a 7-bit Flash ADC. The latter drives a 3rd-order digital filter, which can be configured for different sensor parameters in order to ensure overall loop stability and optimize the noise performance. With a low-noise MEMS sensor, the system achieves a 19-bit DR and a 16-bit SNR, both over a 300Hz bandwidth.

Chaos-based mixed signal implementation of spiking neurons.

Abstract: A new design of Spiking Neural Networks is proposed and fabricated using a 0.35 microm CMOS technology. The architecture is based on the use of both digital and analog circuitry. The digital circuitry is dedicated to the inter-neuron communication while the analog part implements the internal non-linear behavior associated to spiking neurons. The main advantages of the proposed system are the small area of integration with respect to digital solutions, its implementation using a standard CMOS process only and the reliability of the inter-neuron communication.

Reliability Simulation and Circuit-Failure Analysis in Analog and Mixed-Signal Applications

Abstract: In this paper, an effective and efficient methodology for reliability simulation is developed to bridge the gap between device-level reliability and that at product level. For the first time, reliability and circuit-failure behaviors under analog and mixed-signal operating conditions are simulated and analyzed with a high-speed Flash analog-to-digital converter (ADC) circuit developed in advanced CMOS technology. We demonstrate how the failure rate at circuit-level integrating multiple failure mechanisms is determined as a function of operating voltage and temperature. The results show that the dominant failure mechanism and failure rate could be changed by operating conditions. Based on the complete analysis of the ADC circuit operating under normal condition, negative bias temperature instability (NBTI) is the predominant failure mechanism in normal analog and mixed-signal applications, and failure rate increases with the elevated temperature. The impact of NBTI on circuit performance is addressed in detail. Two different types of degradation caused by NBTI are investigated: output voltage degradation and delay. The simulation results are verified by the field data. After exploring the reliability behaviors, a design for reliability methodologies is proposed and classified into two categories: device and circuit levels. This paper shreds light for the circuit life estimation and further reliable design.

60GHz single-chip CMOS digital radios and phased array solutions for gaming and connectivity

Abstract: In this paper, we present four examples of highly integrated 60 GHz single-chip CMOS 90 nm digital radios and phased array solutions. These solutions include for the first time digital-to-analog/analog-to-digital conversion and embedded multi-gigabit mixed signal modem requiring no external processing. This convergence of 60 GHz CMOS digital radio, low power multi-gigabit mixed-signal processing and digital signal processing on a single chip offers the lowest energy per bit transmitted wirelessly at multi-gigabit rate to meet the very stringent low-power specifications for battery operated consumer electronic portable devices. Layout and temperature dependent 60 GHz CMOS 90 nm model development and critical high performance analog and mixed building blocks are presented as fundamental enablers for single chip integration. The designs have been optimized for robustness against process variation and temperature, and verified by measurement results.

Single Event Transient Response of SiGe Voltage References and Its Impact on the Performance of Analog and Mixed-Signal Circuits

Abstract: We investigate the single-event transient (SET) response of bandgap voltage references (BGRs) implemented in SiGe BiCMOS technology through heavy ion microbeam experiments. The SiGe BGR circuit is used to provide the input reference voltage to a voltage regulator. SiGe HBTs in the BGR circuit are struck with 36-MeV oxygen ions, and the subsequent transient responses are captured at the output of the regulator. Sensitive devices responsible for generating transients with large peak magnitudes (more than 5% of the dc output voltage) are identified. To determine the effectiveness of a transistor-layout-based radiation hardened by design (RHBD) technique with respect to immunity to SETs at the circuit level, the BGR circuit implemented with HBTs surrounded by an alternate reverse-biased pn junction (n-ring RHBD) is also bombarded with oxygen ions, and subsequent SETs are captured. Experimental results indicate that the number of events causing transients with peak magnitude more than 5% above the dc level have been reduced in the RHBD version; however, with the inclusion of the n-ring RHBD, new locations for the occurrence of transients (albeit with smaller peak magnitude) are created. Transients at the transistor-level are also independently captured and are presented. It is demonstrated that while the transients are short at the transistor level (ns duration), relatively long transients are obtained at the circuit level (hundreds of nanoseconds). In addition, the impact of the SET response of the BGR on the performance of an ultra-high-speed 3-bit SiGe analog-to-digital converter (ADC) is investigated through simulation. It is shown that ion-induced transients in the reference voltage could eventually lead to data corruption at the output of the ADC.

New Design Methodologies for High Speed Low Power XOR-XNOR Circuits

Abstract: New methodologies for XOR-XNOR circuits are proposed to improve the speed and power as these circuits are basic building blocks of many arithmetic circuits. This paper evaluates and compares the performance of various XOR-XNOR circuits. The performance of the XOR-XNOR circuits based on TSMC 0.18µm process models at all range of the supply voltage starting from 0.6V to 3.3V is evaluated by the comparison of the simulation results obtained from HSPICE. Simulation results reveal that the proposed circuit exhibit lower PDP and EDP, more power efficient and faster when compared with best available XOR-XNOR circuits in the literature. Keywords—Exclusive-OR (XOR), Exclusive-NOR (XNOR), High speed, Low power, Arithmetic Circuits. I. INTRODUCTION HILE the growth of the electronics market has driven the VLSI industry towards very high integration density and system on chip designs and beyond few GHz operating frequencies, critical concerns have been arising to the severe increase in power consumption and the need to further reduce it. Moreover, with the explosive growth the demand and popularity of portable electronics is driving designers to strive for smaller silicon area, higher speeds, longer battery life, and more reliability. Power is one of the premium resources a designer tries to save when designing a system. The XOR- XNOR circuits are basic building blocks in various circuit especially-Arithmetic circuits (Full adder, and multipliers), Compressors, Comparators, Parity Checkers, Code converters, Error-detecting or Error-correcting codes, and Phase detector circuit in PLL. The performance of the complex logic circuits is affected by the individual performance of the XOR-XNOR circuits that are included in them (1)-(6). Therefore, careful design and analysis is required for XOR-XNOR circuits to obtained -full output

Time-mode circuits for analog computation

Abstract: We introduce time-mode circuits, a set of basic circuit building blocks for analog computation using a temporal step function representation for the inputs and outputs. These novel time-mode circuits are low power, provide good noise performance and offer improved dynamic range. The design, IC implementation and detailed theoretical signal-to-noise ratio (SNR) analysis of a prototype time-mode circuit—a weighted average computation circuit—are discussed. This new way of computation is studied with respect to existing conventional voltage-mode and current-mode circuits. Two possible applications of these time-mode circuits are presented: an edge detection circuit for 16 pixels and a 3-tap FIR filter that provides an SNR of 64 dB. Copyright © 2008 John Wiley & Sons, Ltd.

Exact route matching algorithms for analog and mixed signal integrated circuits

Abstract: As SOC designs are getting more popular, the importance of design automation for analog and mixed-signal ICs is increasing. In this paper, we study the problem of exact route matching, which is an important physical design constraint commonly imposed on specific analog signals for the purpose of correct analog functionality. For this, we first propose a mathematical formulation that models the route matching problem exactly. Based on this formulation, we derive important theoretical conclusions, and propose dynamic-programming algorithms to solve the problem. We also discuss how to use heuristic search techniques to enable faster computations. Our experimental results show the effectiveness of our algorithms. Categories and Subject Descriptors B.7.2 [Hardware, Integrated Circuits]: Design Aids General Terms Algorithms, Design

Design of Analog to Digital Converter Using CMOS Logic

Abstract: The real world signals are all analog in nature. The digital signals and digital circuits offer greater advantages as compared to analog circuits in processing speed and efficient transmitting. So in order to convert the analog signals to digital efficiently an “Analog to digital converter” is required. The System on Chip (SoC) forces the analog circuits to be integrated with digital circuits. To follow the scaling down of the SoC trend, analog to digital converter should be operated at low voltages. Thus the idea behind the paper is to design a 3-bit flash ADC using Threshold Inverter Quantization technique with 130nm CMOS technology for high speed and low voltage applications. Threshold Inverter Quantization (TIQ) is a unique way to generate a comparator for a high speed CMOS flash ADC. To improve further, the fat tree encoder that is highly suitable for the ultrahigh speed flash ADCs. A fat tree encoder that has signal delay of “0” is used for better performance. The speed is improved by almost a factor of 2 when using the fat tree encoder. The fat tree encoder is an effective solution for the bottleneck problem in ultra-high speed ADCs. The proposed A/D converter is suitable for System on Chip (SoC) applications in wireless products and other ultra high speed applications.

Self auto-calibration of analog circuits in a mixed signal integrated circuit device

Abstract: Auto-calibration of the analog circuits occurs when requested by a user and/or the occurrence of an event(s). The user may invoke an auto-calibration on demand through an auto-calibration (A CAL ) input to the mixed-signal integrated circuit. An external voltage calibration (V CAL ) input may be used for auto-calibration of the mixed-signal integrated circuit to a user-supplied common-mode voltage reference. Auto-calibration of the mixed-signal integrated circuit may also be initiated upon the occurrence of any one or more of the following events: 1) detection of auto-calibration data corruption, e.g., parity checking of auto-calibration data values digitally stored in the mixed-signal integrated circuit; 2) an internal timer that causes a calibration request after a programmable timeout period, 3) change in the internal integrated circuit die temperature as determined by a temperature sensor, and 4) a change in the power supply and/or internal supply voltage(s).

A mixed-signal organic 1kHz comparator with low V T sensitivity on flexible plastic substrate

Abstract: This paper presents a comparator that is designed in an organic electronics technology on a flexible plastic substrate with p-type organic thin-film transistors (p-OTFT) only. The comparator has a gain of 12dB and works at a supply voltage of 20V consuming 9µA. At a clock frequency of 1kHz the input sensitivity is 200mV. The comparator is designed following a threshold-voltage V T insensitive strategy for analog and mixed-signal design in a way to get round V T variations of the pentacene based organic electronics technology. Measurements have been done in ambient environment. The circuits still function well after several weeks of exposure to ambient environment. This comparator can serve in organic smart sensor systems as an interface between analog sensor signals and digital circuitry or as a building block for more complex A-to-D converters.

Methodology for the Digital Calibration of Analog Circuits and Systems: with Case Studies

Abstract: Methodology for the Digital Calibration of Analog Circuits and Systemsshows how to relax the extreme design constraints in analog circuits, allowing the realization of high-precision systems even with low-performance components.A complete methodology is proposed, andthree applications are detailed. To start with, an in-depth analysis of existing compensation techniques for analog circuit imperfections is carried out. The M/2+M sub-binary digital-to-analog converter is thoroughly studied, and the use of this very low-area circuit in conjunction with a successive approximations algorithm for digital compensation is described. A complete methodology based on this compensation circuit and algorithm is then proposed. The detection and correction of analog circuit imperfections is studied, and a simulation tool allowing the transparent simulation of analog circuits with automatic compensation blocks is introduced. The first application shows how the sub-binary M/2+M structure can be employed as a conventional digital-to-analog converter if two calibration and radix conversion algorithms are implemented. The second application, a SOI 1T DRAM, is then presented. A digital algorithm chooses a suitable reference value that compensates several circuit imperfections together, from the sense amplifier offset to the dispersion of the memory read currents. The third application is the calibration of the sensitivity of a current measurement microsystem based on a Hall magnetic field sensor. Using a variant of the chopper modulation, the spinning current technique, combined with a second modulation of a reference signal, the sensitivity of the complete system is continuously measured without interrupting normal operation. A thermal drift lower than 50 ppm/C is achieved, which is 6 to 10 times less than in state-of-the-art implementations. Furthermore, the calibration technique also compensates drifts due to mechanical stresses and ageing.

Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits

Abstract: A methodology is proposed to efficiently analyze substrate noise coupled to a sensitive block due to an aggressor digital block in large-scale mixed-signal circuits. The methodology is based on identifying voltage domains on the substrate by exploiting the small spatial voltage differences on the ground distribution network of the aggressor circuit. Specifically, similarly biased regions on the substrate short-circuited by the ground network are determined, and each of these regions is represented by a single equivalent input port to the substrate. The remaining ports within that domain are ignored to reduce the computational complexity of the extraction process. An algorithm with linear time complexity is proposed to merge those substrate contacts exhibiting a voltage difference smaller than a specified value, identifying a voltage domain. An equivalent contact is placed at the geometric mean of the merged contacts, ignoring all of the remaining ports such as the source/drain junctions of the devices. The ground network impedance is updated for each merged contact based on the proposed algorithm to maintain sufficient accuracy of the noise voltage. The substrate with reduced input ports is extracted using an existing extraction tool to analyze the noise at the sense node. As compared to the full extraction of an aggressor circuit, the methodology achieves a reduction of more than four orders of magnitude in the number of extracted substrate resistors with a peak-to-peak error of 24%.

Bias-controlled deep trench substrate noise isolation integrated circuit device structures

Abstract: A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip. The deep penetration of the capacitor creates a grounded shield deep in the substrate as compared with other prior art shielding techniques.

Event driven analog modeling for the verification of PLL frequency synthesizers

Abstract: The focus of this work is to provide a efficient modeling approach for the functional verification of complex analog frequency synthesizers. The event driven analog modeling approach uses the double precision data type wreal (supported by VerilogAMS), that enables analog accuracy in the digital simulation domain. It is therefore possible to separate high frequency signal paths in the frequency synthesizers from the analog domain, in order to archive higher simulation efficiency for fast verification purposes. The modeling approach and an investigation of the necessary accuracy requirements for the verification including phase noise performances of the analog frequency synthesizers is presented. The proposed approach is demonstrated on baseof a sub micron CMOS Fractional-N frequency synthesizer and compared with different traditional modeling approaches, like phase model and pure digital model. The paper concludes with a proposal of a verification approach for RF mixed signal systems.

Solid-state storage system with parallel access of multiple flash/pcm devices

Abstract: Systems and methods are provided that confront the problem of failed storage integrated circuits (ICs) in a solid state drive (SSD) by using a fault-tolerant architecture along with one error correction code (ECC) mechanism for random/burst error corrections and an L-fold interleaving mechanism. The systems and methods described herein keep the SSD operational when one or more integrated circuits fail and allow the recovery of previously stored data from failed integrated circuits and allow random/burst errors to be corrected in other operational integrated circuits. These systems and methods replace the failed integrated circuits with fully functional/operational integrated circuits treated herein as spare integrated circuits. Furthermore, these systems and methods improve I/O performance in terms of maximum achievable read/write data rate.

Iterative built-in testing and tuning of mixed-signal/RF systems

Abstract: Design and test of high-speed mixed-signal/RF circuits and systems is undergoing a transformation due to the effects of process variations stemming from the use of scaled CMOS technologies that result in significant yield loss. To this effect, postmanufacture tuning for yield recovery is now a necessity for many high-speed electronic circuits and systems and is typically driven by iterative test-and-tune procedures. Such procedures create new challenges for manufacturing test and built-in self-test of advanced mixed-signal/RF systems. In this paper, key test challenges are discussed and promising solutions are presented in the hope that it will be possible to design, manufacture and test “truly self-healing” systems in the near future.