Showing papers on "RC circuit published in 2004"

H-bridge drive utilizing a pair of high and low side MOSFET's in a common insulation housing

Abstract: A fully protected H-bridge for a d-c motor consists of two high side MOSFETs and a control and logic IC on a first conductive heat sink all within a first package and two discrete low side MOSFETs. The entire bridge is controlled by the IC. Shoot thru protection is provided for each leg, and a PMW soft start sequence is provided through the control of the low side MOSFETs, programed by an external, chargeable RC circuit. Input signals to the high side MOSFETs select the operation modes. Protective circuits are provided for short circuit current and over current conditions. Sleep mode and braking/non braking control is also provided.

A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolution

Abstract: A wide-bandwidth continuous-time sigma-delta ADC is implemented in a 0.13-/spl mu/m CMOS. The circuit is targeted for wide-bandwidth applications such as video or wireless base-stations. The active blocks are composed of regular threshold voltage devices only. The fourth-order architecture uses an OpAmp-RC-based loop filter and a 4-bit internal quantizer operated at 300-MHz clock frequency. The converter achieves a dynamic range of 11 bits over a bandwidth of 15 MHz. The power dissipation is 70 mW from a 1.5-V supply.

A thermal model for insulated gate bipolar transistor module

Abstract: A thermal resistor-capacitor (RC) model is introduced for the power insulated gate bipolar transistor (IGBT) modules used in a three-phase inverter. The parameters of the model are extracted from the experimental data for the transient thermal impedance from-junction-to-case Z/sub jc/ and case-to-ambient Z/sub ca/. The accuracy of the RC model is verified by comparing its predictions with those resulting from the three-dimensional finite element method simulation. The parameter extraction algorithm is easy to adapt to other types of power modules in an industrial application environment.

A compact, timed-shutoff, MOSFET-based power clamp for on-chip ESD protection

Abstract: We present a novel RC-triggered, MOSFET-based power clamp for on-chip ESD protection The cascaded PFET feedback technique is introduced As with other feedback techniques, only a very small time constant is required for the RC trigger circuit which results in reduced capacitor area and reduced leakage at power-up If mistriggering occurs, it is self-corrected with this dynamic feedback technique

Analysis and design considerations of a buck converter with a hysteretic PWM controller

Abstract: This paper presents an analysis and design considerations of a buck converter with a hysteretic PWM controller consist only of a comparator with a hysteresis. The ramp voltage superimposed on the output is supplied to the comparator from a simple RC network connected in parallel to the inductor winding. The steady-state output voltage and the switching frequency are initially examined taking the propagation delay in the control circuit into account. Next, the transfer functions of the output voltage for the input voltage and the load current are analyzed. The transient response of the output voltage for the step load change is also investigated by using the state equation. Furthermore, the design of the time constant of RC networks as a key parameter is discussed.

An RC time constant auto-tuning structure for high linearity continuous-time /spl Sigma//spl Delta/ modulators and active filters

Abstract: An automatic RC time constant tuning scheme is proposed for high linearity continuous-time g/sub m/-C and active RC circuits in a low power consumption environment. Instead of changing the g/sub m/ (in g/sub m/-C filters), the RC time constant is tuned by discretely varying the integration capacitors to preserve a high linearity. The auto-tuning circuit, consisting of an analog integrator, a voltage comparator, and a digital tuning engine, generates a control word and sets on-chip capacitors to obtain an RC time-constant accuracy of /spl plusmn/2-10%. The proposed scheme is verified by the experimental results of a test chip in a 0.5 /spl mu/m CMOS technology. It achieves a peak S/(N+D) of 83 dB while a tuning range of over /spl plusmn/40% is accomplished.

Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees

Abstract: Recent years have seen significant research in finding closed form expressions for the delay of an RC circuit that improves upon the Elmore delay model. However, several of these formulae assume a step excitation, leaving it to the reader to find a suitable extension to ramp-we always refer to saturated ramps in this paper-inputs. The few works that do consider ramp inputs do not present a closed-form formula that works for a wide range of possible input slews. We propose the PERI (probability distribution function extension for ramp inputs) technique, that extends delay metrics for step inputs to the more general and realistic non-step (such as a ramp) inputs. Although there has been little work done in finding good slew (which is also referred as signal transition time) metrics, we also show how one can extend a slew metric for step inputs to the non-step case. We validate the efficacy of our approach through experimental results from several hundred RC dominated nets extracted from an industry application specific integrated circuit design.

Optimized waveform relaxation methods for RC type circuits

Abstract: Waveform relaxation (WR) has been widely used in circuit theory for the solution of large systems of ordinary differential equations, and the solution of partial differential equations. In the past, clever partitioning schemes have been used for circuit applications to enhance convergence. However, a drawback of the classical WR algorithm is the nonuniform convergence over the window in time for which the equations are integrated. We propose a new optimized WR algorithm which greatly accelerates the convergence by introducing new transmission conditions. These conditions are responsible for the exchange of information between the subcircuits. We use two RC circuit examples to illustrate the theory, as well as the improved convergence behavior.

High PSRR, high accuracy, low power supply bandgap circuit

Abstract: A bandgap circuit comprising a current generation circuit and a current replication circuit is provided herein. The output current of the current generation circuit is generated as a weighted sum of two currents. The circuit configuration of the current generation circuit allows it to function at low power supply voltages, e.g., on the order of 1 V. The current replication circuit includes an operational amplifier, which when configured in conjunction with MOS cascode current sources and the current generation circuit, significantly increases the accuracy and insensitivity to power supply noise of the bandgap circuit output current. A resistor may be included between the bandgap circuit output node and ground for generating a reference voltage with increased accuracy and insensitivity to power supply noise.

A self-driven active clamp forward converter using the auxiliary winding of the power transformer

Abstract: This study proposes a new self-driven active clamp forward converter eliminating the extra drive circuit for the active clamp switch. The converter used the auxiliary winding of the power transformer to drive the active clamp switch and a simple RC circuit to get the dead time between the two switches. The operation principle was presented and experimental results were used to verify theoretical predictions. A 100-W (5 V/20 A) prototype converter that only exhibited 1.5-turn winding number in the auxiliary winding was sufficient to drive the active clamp switch on the input of 50 V. Finally, the measured efficiency of the converter was presented and the maximum efficiency of 91% was obtained.

Tuning circuit for a filter

Abstract: The invention relates to a tuning circuit for tuning a filter stage, which has an RC element ( 1 ) with an RC time constant (τ), with the RC time constant (τ) being the product of the resistance of a resistor (R 1 ) in the RC element ( 1 ) and the capacitance of a capacitor (C 1 ), which is connected in series with the resistor (R 1 ), in the RC element ( 1 ), having a comparator ( 10 ) for comparison of the voltage which is produced at the potential node ( 4 ) between the resistor (R 1 ) and the capacitor (C 1 ), with a reference ground voltage; and having a controller ( 15 ) which varies the charge on the capacitor (C 1 ) in the RC element ( 1 ) until the comparator ( 10 ) indicates that the voltage which is produced at the potential node ( 4 ) is equal to the reference ground voltage, with the controller ( 15 ) switching a capacitor array ( 26 ) as a function of the charge variation time, which capacitor array ( 26 ) is connected in parallel with the capacitor (C 1 ) in the RC element ( 1 ), in order to compensate for any discrepancy between the RC time constant (τ) of the RC element ( 1 ) and a nominal value.

Self-driven circuit for synchronous rectifier DC/DC converter

Abstract: A power converter having a primary circuit (e.g. full bridge) and a secondary circuit (e.g. current doubler) has switches in the secondary circuit that are controlled by a drive circuit. The drive circuit is connected to a swing node in the primary circuit, and is powered by the primary circuit. The drive circuit has an isolation device such as a transformer to provide electrical isolation between the primary circuit and secondary circuit. The drive circuit provides a current source for driving the secondary switch gates, thereby reducing power consumption. The present drive circuit provides clean gate drive signals without noise and oscillations. The drive circuits of the invention are simple, and require only a few components.

Overvoltage suppression filter design methods based on voltage reflection theory

Abstract: To reduce voltage overshoot at the motor terminal, RLC filters are used at the inverter side with an objective of increasing the rise time, while RC filters are used at the motor side as a means of reducing the load impedance at high frequency. However, no clear optimal method for determining the filter parameters has appeared. In this work, we propose filter design methods that fully utilize given conditions such as cable length, cable inductance, cable capacitance, and the reflection coefficient at the inverter side. For determining the parameters of the RLC filter, the filter transfer function is utilized to make the rise time long enough to achieve desirable overshoot level at motor terminals. In choosing the parameters of the RC filter, the reflection coefficient is regarded as a transfer function between the incident and reflected voltages, and the capacitance is chosen so that cancellation occurs between the reflected voltage and its resulting incident voltage. The validity of the proposed design method is supported by simulation results, which are also compared with the experimental results.

Feedback loop for LC VCO

Abstract: A voltage-controlled oscillator includes an inductor capacitor (LC) tank; a drive circuit having a current source; and a feedback loop circuit. The feedback loop includes a peak detect circuit to generate a peak detect voltage; a reference voltage generator to generate a single reference voltage; and an operational amplifier, coupled to the peak detect circuit and the reference voltage generator, to generate an analog bias signal to adjust a current of the current source.

Apparatus and method of determining a user selection in a user interface

Abstract: A user interface (210) includes an RC circuit (213). The RC circuit (213) includes a variable capacitance. The variable capacitance is produced by a sensing member (310) in cooperation with a user's finger (311). When a user makes a selection with the user interface (210), the user places a finger (311) in close proximity and in a facing relationship to a section, or discrete surface (320, 322, 324), of the sensing member (310). The discrete surfaces (320, 322, 324) can correspond to keys of a keypad (138) or to directions of a directional button (1030), for example. The time constant of the RC circuit (213) varies according to which discrete surface (320, 322, 324) is determining the capacitance of the RC circuit (213). A controller (118) determines the user's selection based on the time constant of the RC circuit (213).

A delay metric for RC circuits based on the Weibull distribution

Abstract: Physical synthesis optimizations require fast and accurate analysis of RC networks. Elmore first proposed matching circuit moments to a probability density function (PDF), which led to widespread adoption of his simple and fast metric. The more recently proposed PRIMO and H-gamma metrics match the circuit moments to the PDF of a Gamma statistical distribution. We instead propose to match the circuit moments to a Weibull distribution and derive a new delay metric called Weibull-based delay (WED). The primary advantages of WED over PRIMO and H-gamma are its efficiency and ease of implementation. Experiments show that WED is robust and has satisfactory accuracy at both near- and far-end nodes.

Effective number of resolution bits in direct sensor-to-microcontroller interfaces

Abstract: Microcontrollers with embedded timers can directly measure resistive and capacitive sensors by determining the charging or discharging time of an RC circuit that includes the sensor. This time-to-digital conversion is affected by the quantization of the timer and the trigger noise, which limit the resolution to an effective number of bits (ENOB). This paper analyses the standard uncertainty and the ENOB of that time-to-digital conversion. When interfacing resistive sensors and the capacitor C is small, quantization effects predominate over trigger noise effects, and ENOB increases for increasing C. But, for capacitor values larger than a given C, trigger noise effects predominate and the ENOB remains constant regardless of C. Therefore, an optimal time constant yields the best speed–ENOB trade-off. This type of sensor interface was implemented by using an AVR microcontroller with an embedded 16-bit timer connected to a resistor simulating a Pt1000-type temperature sensor. The experimental results agree with the theoretical predictions. If the time was determined from a single observation, the optimal time constant was about 2–3 ms and the ENOB was about 11.5 b, which corresponds to a 0.22 Ω resolution. By averaging ten observations, that resolution improved to 13.5 b (0.05 Ω).

A low-cost microcontroller interface for low-value capacitive sensors

Abstract: Microcontrollers with embedded timers can measure resistances or capacitances by determining the charging or discharging time of an RC circuit. The microcontroller-based interfaces proposed for capacitive sensors have not been analyzed in detail, and basic information such as capacitance range, stray capacitance compensation, and accuracy is not available. This paper analyzes the performance of these interfaces when measuring capacitances in the picofarad range. The effects of stray capacitances are evaluated and reduced by applying the three-signal calibration technique. For the PIC16F873 microcontroller, the absolute error achieved is below 4% FSR for 1 pF < C/sub x/ < 10 pF, and below 1.5% for 10 pF < C/sub x/ < 100 pF.

Novel automatic tuning method of RC filters using a digital-DLL technique

Abstract: A novel automatic tuning method for RC filters is proposed for CMOS low-IF transceivers. The method is based on a digital-DLL-like technique and tunes the time constant of filters automatically. The tuning range and the tuning accuracy are analyzed theoretically. To verify the method, a sixth-order 2-MHz IF filter for Bluetooth and a tuning circuit were fabricated in 0.18-/spl mu/m CMOS. The tuning circuit occupying 0.066 mm/sup 2/ includes only a reference first-order filter, a comparator, and a simple digital circuit. The measurement result of the filter and the tuning circuit shows that the maximum /spl plusmn/28% time-constant variation can be tuned within /spl plusmn/5% accuracy, which is consistent with theoretical results.

Evaluation of energy consumption in RC ladder circuits driven by a ramp input

Abstract: In this paper, the energy consumption of RC ladder networks, which can represent chains of transmission gate or long wire interconnections, is modeled. Their energy dependence on the input rise time is analyzed by assuming a ramp input waveform. Since the analysis can be carried out in a straightforward manner only for very simple RC ladder networks, the exact analysis is first limited to asymptotic values of the input rise time T (i.e., for T/spl rarr/0 and T/spl rarr//spl infin/). Successively, the energy expression is extended to arbitrary values of the input rise time by introducing a suitable equivalent first-order RC circuit, whose resistance and capacitance are simply related to the resistances and capacitances of the original network. The energy expression found is useful for pencil-and-paper evaluation and affords an intuitive understanding of the network dissipation, since each term has an evident physical meaning. By comparison with SPICE simulations, the energy expression proposed is showed to be accurate enough for modeling purposes.

Differential transmission line interconnect for high speed and low power global wiring

Abstract: This paper proposes transmission line interconnect, which achieves high speed and low power consumption for global interconnects. The delay time and power consumption are evaluated at 4 Gbps signal frequency. RLC differential transmission line is faster than RC line when interconnect length is over 2.4 mm. RLC line has lower power consumption than RC line over 7.0 mm. Increasing interconnect area can be suppressed by using the diagonal-pair line structure as the differential transmission line.

Accurate testing of ADC's spectral performance using imprecise sinusoidal excitations

Abstract: Analog to digital converter (ADC) is the world's largest volume mixed-signal circuit. It is also a key building block in nearly all system on chip (SoC) solutions involving analog and mixed-signal functionalities. ADC testing is also crucial for built-in-self-test (BIST) solutions of AMS testing in SoC technology which is identified by the ITRS as one of four most daunting SoC challenges. ADC spectral testing is of critical importance to a large class of integrated circuits and is particularly challenging for high speed and/or high resolutions circuits. In this paper we use spectrally related excitations (SRE) to accurately test the spectral performance of ADCs. Unlike standard approaches, the SRE approach uses low-cost imprecise sine signals as input to the ADC and uses the spectral relationship between multiple input signals to separate distortion inherent in the ADC from that in the input. Efficient DSP algorithms are used to determine the true spectral performance of the ADC. This approach works in both production test and BIST environments. Simulation results show two sine waves with < 60 dB purity can be used to accurately test spectral performance of high resolution ADCs with SFDR in excess of 100 dB. The low-cost SRE signals can be readily generated with simple RC filters with lax band edge requirements. Extensive simulation shows that the algorithm is robust to filter errors, to nonstationary in the test environment, and to measurement noise.

A simple metric for slew rate of RC circuits based on two circuit moments

Abstract: In this paper, we introduce a simple metric for the slew rate of an RC circuit based on the first two circuit moments. Metrics focusing on 50% delay of RC circuits have been proposed recently that greatly improve the accuracy of the traditional Elmore delay model. However, these new models have not been applied to the determination of transition time or slew rates (e.g., 10-90% of V/sub dd/). We study how well existing approaches to 50% delay modeling translate to slew-rate modeling. We first describe a new metric called slew with two moments (S2M) that is based on Elmore's observation that the transition time of a step response is proportional to the standard deviation of the corresponding impulse response. The S2M metric modifies Elmore's original formulation by deriving a new constant of proportionality. This new constant is shown to be more accurate for general RC circuits. Next, we show that metrics relying on a simple constant multiplied by standard deviation such as S2M and Elmore do not work well for near-end nodes. To address this issue, we propose a new slew metric called scaled S2M that provides high accuracy across all types of nodes, while maintaining the advantage of a simple closed-form expression. Scaled S2M is shown to be very accurate for both near and far-end nodes. The average error for scaled S2M is approximately 2% with 96% of all nodes showing less than 5% error from a large set of industrial 0.18-/spl mu/m microprocessor nets.

On optimality of adiabatic switching in MOS energy-recovery circuit

Abstract: The principle of adiabatic switching in conventional energy-recovery adiabatic circuit is generally explained with the help of a rudimentary RC circuit being driven by a constant current source. However, it is not strictly accurate to approximate a MOS adiabatic circuit by such an elementary model owing to its failure to incorporate the nonlinearity of very deep sub-micron transistors. This paper employs the theory of variational calculus in order to extend the principle of optimality used in this RC model to general MOS adiabatic circuits. Our experimental results include energy dissipation comparison in various adiabatic schemes using optimal power clocking versus other waveforms.

AC testing of leakage current in integrated circuits using RC time constant

Abstract: A method of testing an integrated circuit includes applying a voltage to one of the pins of the integrated circuit. The pin is floated for a predetermined time. A measurement is performed after the predetermined time. The measurement involves sampling the RC time constant of leakage current of the pins.

Synchronous rectifier with dead time adjusting function

Abstract: A synchronous rectifier with dead time adjusting function is used in fly-back power supplies for adjusting dead time of switches. The synchronous rectifier has a rectifying circuit connected to a secondary side terminal of a transformer and outputting a positive half-cycle voltage, a charging circuit connected to the rectifying circuit for producing a first charging voltage and a second charging voltage, a regulated power circuit connected to the charging circuit and producing a reference voltage, a trigger circuit connected to the rectifying circuit and the charging circuit for generating a dead time adjusting comparing signal, a comparing circuit connected to the regulated circuit, the charging circuit and the trigger circuit for producing a dead time adjusting signal, and a logic circuit connected to the comparing circuit and the rectifying circuit for outputting a driving signal for controlling on/off states of a first electric switch.

Active clamping circuit and power supply system using the same

Abstract: An active clamping circuit. The active clamping circuit is applicable to a DC-to-DC conversion circuit, and has an output terminal to supply an output voltage to a load. In the active clamping circuit, a determining circuit is coupled to the DC-to-DC conversion circuit to determine the output detects the output voltage and to output a first enable signal when the output voltage is higher than a first predetermined voltage. A voltage adjustment circuit is coupled to the determining circuit to pull low the output voltage according to the first enable signal. An inductor has a first end coupled to the output terminal of the DC-to-DC conversion circuit, and a diode is coupled between the inductor and an input terminal of the DC-to-DC conversion circuit as a conductive path to channel discharge current to the input terminal of the DC-to-DC conversion circuit.

Analytical ramp delay model for distributed on-chip RLC interconnects

Abstract: In the past, gate delay was the dominant factor in determining circuit performance. However, as feature size becomes smaller and chip area becomes larger in integrated circuits, interconnect delay has become an increasingly important factor in determining circuit performance. In this paper, we present an analytical delay calculation approach for a distributed RLC interconnect line that maintains the effectiveness and the efficiency of past RC interconnect models, but significantly improving their accuracy for deep submicron (DSM) designs.

Study of ultracapacitors dynamic behaviour using impedance frequency analysis on a specific test bench

Abstract: This paper presents a study on the ultracapacitors dynamic behaviour. Frequency analysis is chosen as the tool to perform this investigation. First, the impedance spectroscopy principles are presented. Then the experimental results, obtained by applying impedance spectroscopy with high current levels, are presented and discussed. Ultracapacitors show a particular behaviour which leads to it specific model composed by a small serial inductance associated with a four RC-branches network.