Showing papers on "Transistor published in 1991"

Semiconductor physics and devices

Abstract: Neamen's Semiconductor Physics and Devices, Third Edition. deals with the electrical properties and characteristics of semiconductor materials and devices. The goal of this book is to bring together quantum mechanics, the quantum theory of solids, semiconductor material physics, and semiconductor device physics in a clear and understandable way. Table of contents Prologue Semiconductor and the Integrated Circuit 1 The Crystal Structure of Solids 2 Introduction to Quantum Mechanics 3 Introduction to the Quantum Theory of Solids 4 The Semiconductor in Equilibrium 5 Carrier Transport Phenomena 6 Nonequilibrium Excess Carriers in Semiconductors 7 The pn Junction 8 The pn Junction Diode 9 Metal-Semiconductor and Semiconductor Heterojunctions 10 The Bipolar Transistor 11 Fundamentals of the Metal-Oxide-Semiconductor Field-Effect Transistor 12 Metal-Oxide-Semiconductor Field-Effect Transistor: Additional Concepts 13 The Junction Field-Effect Transistor 14 Optical Devices 15 Semiconductor Power Devices Appendix A Selected List of Symbols Appendix B System of Units, Conversion Factors, and General Constants Appendix C The Periodic TableAppendix D The Error FunctionAppendix E "Derivation" of Schrodinger's Wave EquationAppendix F Unit of Energy- The Electron-VoltAppendix G Answers to Selected Problems

Improved Analysis of Low Frequency Noise in Field‐Effect MOS Transistors

Abstract: An improved analysis of low frequency trapping noise in a MOS device is proposed. This analysis takes into account the supplementary fluctuations of the mobility induced by those of the interface charge. It enables an adequate description of the gate voltage dependence of the input equivalent gate voltage noise to be obtained in various actual situations. The outputs given by the Hooge mobility fluctuation model are also presented and discussed with respect to those obtained by the carrier number fluctuation model. In particular, the impact of the channel length or channel width, and the model type on the input gate voltage and drain current noise characteristics is studied and compared to typical experimental data. Finally, a procedure for the diagnosis of the low frequency noise sources in a MOS transistor is proposed.

A neuron-silicon junction: a Retzius cell of the leech on an insulated-gate field-effect transistor.

Abstract: An identified neuron of the leech, a Retzius cell, has been attached to the open gate of a p-channel field-effect transistor. Action potentials, spontaneous or stimulated, modulate directly the source-drain current in silicon. The electronic signals match the shape of the action potential. The average voltage on the gate was up to 25 percent of the intracellular voltage change. Occasionally weak signals that resemble the first derivative of the action potential were observed. The junctions can be described by a model that includes capacitive coupling of the plasma membrane and the gate oxide and that accounts for variable resistance of the seal.

The potential of diamond and SiC electronic devices for microwave and millimeter-wave power applications

Abstract: The potential of SiC and diamond for producing microwave and millimeter-wave electronic devices is reviewed. It is shown that both of these materials possess characteristics that may permit RF electronic devices with performance similar to or greater than what is available from devices fabricated from the commonly used semiconductors, Si, GaAs, and InP. Theoretical calculations of the RF performance potential of several candidate high-frequency device structures are presented: the metal semiconductor field-effect transistor (MESFET), the impact avalanche transit-time (IMPATT) diode, and the bipolar junction transistor (BJT). Diamond MESFETs are capable of producing over 200 W of X-band power as compared to about 8 W for GaAs MESFETs. Devices fabricated from SiC should perform between these limits. Diamond and SiC IMPATT diodes also are capable of producing improved RF power compared to Si, GaAs, and InP devices at microwave frequencies. RF performance degrades with frequency and only marginal improvements are indicated at millimeter-wave frequencies. Bipolar transistors fabricated from wide bandgap material probably offer improved RF performance only at UHF and low microwave frequencies. >

Making and testing an integrated circuit using high density probe points

Abstract: Each transistor or logic unit on an integrated wafer (1) is tested prior to interconnect metallization. By means of CAD software, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD computer syste. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than wich conventional testing at the completed circuit level. The individual transistor or logic unit testing is accomplished by specially fabricated flexible tester surface (10) made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points (15-1, 15-2) on one side of the test surface (10). The probe points (330) electrically contact the contacts (2-1, 2-2) on the wafer (1) under test by fluid pressure.

Fundamentals of Solid State Electronics

Abstract: Electrons, bonds, bands and holes homogeneous semiconductor at equilibrium drift, diffusion, generation, recombination, trapping and tunneling metal-oxide-semiconductor capacitor P/N and other junction diodes metal-oxide-semiconductor and other field-effect transistors bipolar junction transistor and other bipolar transistor devices.

Applications of Quantum Semiconductor Structures

Abstract: This chapter discusses the applications of quantum semiconductor structures A new heterostructure type of FET has been developed that includes the two-dimensional electron gas field effect transistor also called high electron mobility transistor, modulation doped field effect transistor, or selectively doped heterojunction transistor depending on manufacturer It has features in common with both MESFETs and metal-oxide-silicon field effect transistors The structure is based on the heterojunction between AlGaAs and GaAs Its essential structure consists of a semi-insulating substrate on which is first grown a buffer layer of nonintentionally doped GaAs and on top of this is grown a thin layer of Al x Ga 1− x As, part of which is rather heavily n-type doped The gate metal forms a Schottky barrier to the AlGaAs and by making the ternary layer thin enough, the gate can completely deplete the AlGaAs layer of electrons Then the density of electrons on the GaAs side of the heterojunction is controlled by the voltage applied to the gate, so that the current between the source and the drain contacts can be controlled by the gate voltage

Impact of surrounding gate transistor (SGT) for ultra-high-density LSI's

Abstract: A transistor with compact structures for future MOS devices is discussed. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. By using this transistor, the occupied area of the CMOS inverter can be shrunk to 50% of that using planar transistors. Other advantages, such as steep cutoff characteristics, very small substrate bias effects, and high reliability, are discussed. Its structure, which allows for the enlargement of gate-controllability to the channel and electric field relaxation at the drain edge, is described. The advantages of this SGT for large-scale integration (LSI) devices is discussed. >

Realization of high breakdown voltage (>700 V) in thin SOI devices

Abstract: The avalanche breakdown voltage of silicon on insulator (SOI) lateral diodes is investigated theoretically and experimentally. Theoretically, a condition is derived for achieving a uniform lateral electric field and thus optimizing the breakdown voltage. Using this condition, it is shown that, for SOI thicknesses below about 1 mu m, diode breakdown voltage increases with decreasing SOI layer thickness. Experimentally, breakdown voltages in excess of 700 V have been demonstrated for the first time on diodes having approximately 0.1- mu m-thick SOI layers and 2- mu m-thick buried oxide layers. The results obtained demonstrate the feasibility of making high-voltage thin-film SOI LDMOS transistors and, more importantly, the ability to integrate such devices with high-performance ultra-thin SOI CMOS circuits on a single chip. >

High-frequency equivalent circuit of GaAs FETs for large-signal applications

Abstract: The application of GaAs field effect transistors in digital circuits requires a valid description by an equivalent circuit at all possible gate and drain bias voltages for all frequencies from DC up to the gigahertz range. An equivalent circuit is presented which takes into account the gate current of positively biased transistors as well as the symmetrical nature of the devices at low drain voltages. A fast method of determining the elements of the equivalent circuit at all bias points without frequency limitations is presented. Direct computation from analytical expressions, without iteration, allows this parameter extraction procedure to be used for real-time on-wafer parameter extraction. Large-signal calculations are possible by inserting the voltage dependences evaluation for the elements into suitable simulation programs, such as SPICE. >

A MOS gate drive with resonant transitions

Abstract: A resonant gate-drive circuit for MOS power transistors is described. The gate drive provides quasi-square-wave gate-to-source voltage with low impedance between gate and source terminals in both on and off states. Input capacitance of the power MOS transistor is charged and discharged in a resonant circuit so that switching losses in the gate drive are eliminated. This is particularly important in high-frequency and low-power applications. A detailed loss analysis yields closed-form solutions for gate-drive and total switch losses. These results are used to select the MOS power transistor with minimum losses, and to compare the gate drive with resonant transitions against the conventional gate drive. >

Thin-layer field-effect transistors with MIS structure whose insulator and semiconductor are made of organic materials

Abstract: A thin-layer field-effect transistor (TFT) with an MIS structure includes a thin semiconductor layer between a source and a drain. The thin semiconductor layer is in contact with one surface of a thin layer made of insulating material, and in contact by its other surface with a conducting grid. The semiconductor is composed of at least one polyconjugated organic compound with a specific molecular weight. The polyconjugated organic compound or polyconjugated organic compounds contain at least 8 conjugated bonds and have a molecular weight of no greater than approximately 2,000. The thin layer of insulating material is made of an insulating organic polymer having a dielectric constant of at least equal to 5. The transistor is useful as a switching or amplifying element.

Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories

Abstract: This invention constitutes a 10-12 mask, split-polysilicon process for fabricating dynamic random access memories of the stacked capacitor type for the one-megabit generation and beyond. The process flow is characterized: reduced mask count due to the elimination of the N+ and p+ source-drain masking layers via the split polysilicon technique; an option to further reduce wafer processing by allowing the LOCOS stress relief (pad) oxide layer to later function as the transistor gate dielectric layer; N-channel device optimization via self-aligned punch-through and lightly-doped-drain (LDD) implants, without the addition of extra P-channel masking steps via the split poly approach; use of semi, self-aligned contact of bottom cell plate to access gate diffusion allowing tight spacing between bottom cell plate buried contact and access gate polysilicon; improved refresh characteristics achieved by avoiding reduction of isolation thickness due to the spacer oxide etch; improved refresh characteristics achieved by protecting the sensitive areas of the storage node from damage typically caused by a spacer oxide etch; improved refresh characteristics achieved by eliminating the high-dose N-channel source/drain implantation from the storage node side of the access transistor gate; and improved immunity to soft error upset achieved through the use of an optional self-aligned "Hi-C" implant that is performed without the addition of an extra masking step.

High-gain lateral bipolar action in a MOSFET structure

Abstract: A hybrid-mode device based on a standard submicrometer CMOS technology is presented. The device is essentially a MOSFET in which the gate and the well are internally connected to form the base of a lateral bipolar junction transistor (BJT). At low collector current levels, lateral bipolar action with a current gain higher than 1000 is achieved. No additional processing steps are needed to obtain the BJT when the MOSFET is properly designed. n-p-n BJTs with a 0.25- mu m base width have been successfully fabricated in a p-well 0.25- mu m bulk n-MOSFET process. The electrical characteristics of the n-MOSFET and the lateral n-p-n BJT at room and liquid nitrogen temperatures are reported. >

Light valve device

Abstract: A light valve has a composite substrate comprised of an electrically insulating substrate and a semiconductor single crystal thin film formed over the electrically insulating substrate. A pixel array comprising semiconductor switch elements is formed in the semiconductor single crystal thin film. A peripheral circuit having circuit elements is formed in the semiconductor single crystal thin film so that a small-sized, high speed light valve is obtained. X- driver and Y-driver circuits are formed in the semiconductor single crystal thin film and controlled by a control circuit, such as a video signal processing circuit, which receives and processes video signals inputted directly from an external source. The peripheral circuit can be a DRAM sense amplifier for sensing charges stored in each pixel of the pixel array to detect defects in the pixel array. The peripheral circuit can be a photosensor circuit for detecting an intensity of incident light to monitor the performance of a light source of the light valve. The peripheral circuit can be a temperature sensor for detecting the temperature of a liquid crystal layer of the light valve, and may be comprised of Darlington connected NPN transistors formed in the semiconductor single crystal thin film. The peripheral circuit can also be a solar cell for converting incident light into electrical energy to supply power to at least one of the pixel array, X-driver and Y-driver circuits and the peripheral circuit.

Direct extraction of the AlGaAs/GaAs heterojunction bipolar transistor small-signal equivalent circuit

Abstract: The authors describe a novel, direct technique for determining the small-signal equivalent circuit of a heterojunction bipolar transistor (HBT). The parasitic elements are largely determined from measurements of test structures, reducing the number of elements determined from measurements of the transistor. The intrinsic circuit elements are evaluated from y-parameter data, which are DC-embedded from the known parasitics. The equivalent-circuit elements are uniquely determined at any frequency. The validity of this technique is confirmed by showing the frequency independence of the extracted circuit elements. The equivalent circuit models the HBT s-parameters over a wide range of collector currents. Throughout the entire 1-18-GHz frequency range, the computed s-parameters agree very well with the experimental data. >

Impact of the vertical SOI 'DELTA' structure on planar device technology

Abstract: A fully depleted lean channel transistor (DELTA) with its gate incorporated into a new vertical ultrathin silicon-on-insulator (SOI) structure is presented. In the deep-submicrometer region, selective oxidation produces and isolates an ultrathin SOI MOSFET that has high crystalline quality, as good as that of conventional bulk single-crystal devices. Experiments and three-dimensional simulations have shown that this new gate structure has effective channel control and that the vertical ultrathin SOI structure provides superior device characteristics: reduction in short-channel effects, minimized subthreshold swing, and high transconductance. >

Switched-current circuit design issues

Abstract: Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5%. >

Self-aligning contact and interconnect structure

Abstract: An MOS transistor for use in an integrated circuit is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from a short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of doped polysilicon covered by titanium silicide encapsulated by a thin film of titanium nitride.

Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits

Abstract: The M-SGT has a three-dimensional structure, which consists of the source, gate, and drain arranged vertically. The gate electrode surrounds the crowded multipillar silicon islands. Because all the sidewalls of the pillars are used effectively as the transistor channel, the M-SGT has a high-shrinkage feature. The area occupied by the M-SGT can be shrunk to less than 30% of that occupied by the planar transistor. The small occupied area and the mesh-structured gate electrode lead to the small junction capacitance and the small gate electrode RC delay, resulting in high-speed operation. The fabrication of the M-SGT CMOS inverter chain is discussed. The propagation delay reduces to 40%, compared with the planar transistor inverter chain. >

High voltage boosted word line supply charge pump and regulator for DRAM

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by Vtn as in the prior art. The boosting capacitors are charged by Vdd, thus eliminating drift tracking problems associated with clock boosting sources and Vdd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

An intelligent MOS transistor featuring gate-level weighted sum and threshold operations

Abstract: A novel functional MOS transistor which behaves much more intelligently than a mere switching device has been developed The device has a floating gate whose potential is controlled by a plural number of input gates via capacitive coupling The transistor is called a 'neuron MOSFET' due to its similarity to biological neurons in that the transistor turns on when the weighted sum of all input signals exceeds a certain threshold value Test devices were fabricated using a double-polysilicon NMOS process The analysis of the basic device operation and its experimental verification are presented A number of interesting applications of the neuron MOSFET are described which include a variable threshold transistor, a neuron circuit, a single-gate D/A (digital-to-analog) converter, and a soft hardware logic circuit >

DRAM Cell with trench capacitor and vertical channel in substrate

Abstract: A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate. The transistor source and drain are insulated from the substrate, and the transistor may be adjacent the trench or on the upper portion of the trench sidewalls. Signal charge is stored on the capacitor plate insulated from the substrate.

MOS-type semiconductor integrated circuit device

Abstract: A MOS-type semiconductor integrated circuit device is provided in which MOS transistors are formed in a vertical configuration. The MOS transistors are constituted by pillar layers formed on the substrate. The outer circumferential surfaces of the pillar layers are utilized to form the gates of the MOS transistors. Thus, large gate widths thereof can be obtained within a small area. As a result, the total chip area of the MOS transistors can be significantly reduced while maintaining a prescribed current-carrying capacity.

Extremely high gain 0.15 mu m gate-length InAlAs/InGaAs/InP HEMTs

Abstract: High electron mobility transistors (HEMTs) based on the InAlAs/InGaAs heterojunction grown lattice matched to InP were fabricated with 0.15 μm T-shaped gates. The use of an undoped InGaAs cap layer in the epitaxial structure leads to excellent gate characteristics and very high transistor gain. At 95 GHz, a maximum available gain of 13.6 dB was measured. A maximum frequency of oscillation fmax of 455 GHz was obtained by extrapolating from 95 GHz at –6 dB/octave. This is the best reported gain performance for any transistor.

Non-local impact ionization in silicon devices

Abstract: In small bipolar and MOS transistors, the electrons gain much less energy than according to the maximum electric field. This is due to nonlocal electron heating and the small width of the E-field peak. The simplified energy balance equation with the energy relaxation length lambda /sub e/ as parameter gives the electron temperature for a given electric field distribution. From a series of MBE (molecular beam epitaxy)-grown bipolar transistors and scaled submicron MOS transistors, lambda /sub e/=650 AA was found. With the calculated temperature distribution and known empirical models for the impact ionization, avalanche (substrate) currents are accurately predicted. This procedure can easily be implemented, as postprocessing, in existing device simulators with hardly any extra computation time. It extends in a consistent way the validity range of these simulators to future device generations. >

DSP based space vector PWM for three-level inverter with DC-link voltage balancing

Abstract: The authors describe a novel PWM (pulse width modulation) method for a three-level inverter considering the DC link capacitor balancing problem. Each voltage vector on the space vector plane is classified in relation to the charging/discharging action of DC capacitors, and a novel modulation method is suggested based on the voltage vector selection principle. The algorithm was implemented on the Motorola DSP 56000 and tested with the 7.5 kVA prototype three-level transistor inverter. The effectiveness of the proposed PWM method was verified by the experimental results. It was shown that the proposed PWM techniques are suitable for a high-power GTO (gate turn-off thyristor) three-level inverter satisfying capacitor voltage balancing. >

A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology

Abstract: A 54 b*54 b multiplier fabricated in a double-metal 0.5 mu m CMOS technology is described. The 54 b*54 b full array is adopted to complete multiplication within one latency. A 10 ns multiplication time is achieved by optimizing both the propagation time of the part consisting of 4-2 compressors and the propagation time of the final adder part. The n-channel pass-transistor circuit and the p-channel load circuit are used at the critical blocks to improve the multiplication speed. This multiplier is intended to be applied to double-precision floating-point data processing based on the IEEE standard up to clock range of 100 MHz. >

Fermi threshold silicon-on-insulator field effect transistor

Abstract: A silicon-on-insulator (SOI) field effect transistor (FET) operates in the enhancement mode without requiring inversion by setting the device's threshold voltage to twice the Fermi potential of the thin semiconductor layer in which the transistor is fabricated. The FET, referred to as a Fermi Threshold SOI FET or Fermi SOI FET, has a threshold voltage which is independent of oxide thickness, channel length, drain voltage and substrate channel doping. The vertical electric field in the substrate channel becomes zero, thereby maximizing carrier mobility, and minimizing hot electron effects. The thin silicon layer in which the devices are formed is sufficiently thick such that the channel is not fully depleted at pinch-off. A high speed device, substantially independent of device dimensions is thereby provided, which may be manufactured using relaxed groundrules, to provide low cost, high yield devices. Temperature dependence of threshold voltage may also be eliminated by providing a semiconductor gate contact which neutralizes the effect of substrate contact potential. Multiple gate devices may be provided. An accelerator gate, adjacent the drain, may further improve performance.

Double-edge-triggered D-flip-flops for high-speed CMOS circuits

Abstract: Two circuits are proposed for double edge-triggered D flip-flops (DETDFFs). A DETDFF responds to both edges of the clock pulse. As compared with positive or negative edge-triggered flip-flops, a DETDFF has advantages in terms of power dissipation and speed. Delay figures for these circuits are measured by simulation. It is shown that these circuits are faster and have lower transistor counts than previously reported circuits. It is shown that these flip-flops can be used at 320-400-MHz clock frequency in a 2- mu m technology. >